參數(shù)資料
型號: AT91SAM9261SB-CU
廠商: Atmel
文件頁數(shù): 9/39頁
文件大?。?/td> 0K
描述: IC ARM9 MPU 217-LFBGA
標(biāo)準(zhǔn)包裝: 126
系列: AT91SAM
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 190MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 1.32 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 217-LFBGA
包裝: 托盤
配用: AT91SAM9261-EK-ND - KIT EVAL FOR AT91SAM926EJ-S
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
17
6242ES–ATARM–11-Sep-09
AT91SAM9261S
8.1.1
Internal Memory Mapping
Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
Note:
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
8.1.1.1
Internal SRAM
The AT91SAM9261S embeds a high-speed 16-Kbyte SRAM.
8.1.1.2
Internal ROM
The AT91SAM9261S integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is
also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.
8.1.1.3
USB Host Port
The AT91SAM9261S integrates a USB Host Port Open Host Controller Interface (OHCI). The
registers of this interface are directly accessible on the AHB Bus and are mapped like a standard
internal memory at address 0x0050 0000.
8.1.1.4
LCD Controller
The AT91SAM9261S integrates an LCD Controller. The interface is directly accessible on the
AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted for each Master of the Bus Matrix. Refer to the
Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 15.
The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the
BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
Table 8-3.
Internal Memory Mapping
Address
Master 0: ARM926 Instruction
Master 1: ARM926 Data
REMAP(RCB0) = 0
REMAP (RCB0) = 1
REMAP (RCB1) = 0
REMAP (RCB1) = 1
BMS = 1
BMS = 0
BMS = 1
BMS = 0
0x0000 0000
Int. ROM
Int. RAM C
Int. ROM
EBI NCS0(1)
Int. RAM C
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