參數(shù)資料
型號: AT91SAM7SE32-AU
廠商: Atmel
文件頁數(shù): 27/47頁
文件大?。?/td> 0K
描述: MCU ARM 32K HS FLASH 128-LQFP
產(chǎn)品培訓模塊: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
產(chǎn)品變化通告: AT91SAM7SE32 Obsolescence 10/May/2012
標準包裝: 72
系列: SAM7SE
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 55MHz
連通性: EBI/EMI,I²C,SPI,SSC,UART/USART,USB
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
配用: AT91SAM7SE-EK-ND - EVAL BOARD FOR AT91SAM7SE
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
33
6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
9.5
Debug Unit
Comprises:
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
Two-pin UART
– USART-compatible User Interface
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Debug Communication Channel Support
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of
peripherals
– Chip ID is 0x272A 0A40 (VERSION 0) for SAM7SE512
– Chip ID is 0x272A 0940 (VERSION 0) for SAM7SE256
– Chip ID is 0x2728 0340 (VERSION 0) for SAM7SE32
9.6
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
9.7
Watchdog Timer
12-bit key-protected Programmable Counter running on prescaled SLCK
Provides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode
9.8
Real-time Timer
32-bit free-running counter with alarm running on prescaled SLCK
Programmable 16-bit prescaler for SLCK accuracy compensation
9.9
PIO Controllers
Three PIO Controllers. PIO A and B each control 32 I/O lines and PIO C controls 24 I/O lines.
Fully programmable through set/clear registers
Multiplexing of two peripheral functions per I/O line
For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)
– Input change interrupt
– Half a clock period glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
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