參數(shù)資料
型號: AT91RM9200-CI-002
廠商: Atmel
文件頁數(shù): 26/41頁
文件大?。?/td> 0K
描述: IC ARM9 MCU 256 BGA
標(biāo)準(zhǔn)包裝: 126
系列: AT91
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 180MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: POR
輸入/輸出數(shù): 122
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-BGA
包裝: 托盤
32
1768MS–ATARM–09-Jul-09
AT91RM9200
– Interval Measurement
– Pulse Generation
–Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Internal interrupt signal
Two global registers that act on all three TC Channels
The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to
TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock
(MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. For details, see ”Clock
Control” on page 488.
Table 10-6 gives the correspondence between the Timer Counter clock inputs and clocks in
the AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration.
10.19 MultiMedia Card Interface
Compatibility with MultiMedia Card Specification Version 2.2
Compatibility with SD Memory Card Specification Version 1.0
Cards clock rate up to Master Clock divided by 2
Embedded power management to slow down clock rate when not used
Supports two slots
– One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card
Support for stream, block and multi-block data read and write
Connection to a Peripheral DMA Controller (PDC) channel
– Minimizes processor intervention for large buffer transfers
Table 10-6.
Timer Counter Clocks Assignment
TC Clock Input
Clock
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
TIMER_CLOCK5
SLCK
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