參數(shù)資料
型號: AT90PWM1-16MUR
廠商: Atmel
文件頁數(shù): 29/90頁
文件大?。?/td> 0K
描述: MCU AVR 8K ISP FLASH 16MHZ 32QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標準包裝: 1
系列: AVR® 90PWM 照明
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 19
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 剪切帶 (CT)
其它名稱: AT90PWM1-16MURCT
35
4378C–AVR–09/08
AT90PWM1
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
35 for details.
7.9
Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when chip clock is used to drive other circuits on the system. The clock will be output
also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-
grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output (CKOUT Fuse programmed).
7.10
System Clock Prescaler
The AT90PWM1 system clock can be divided by setting the Clock Prescale Register – CLKPR.
This feature can be used to decrease power consumption when the requirement for processing
power is low. This can be used with all clock source options, and it will affect the clock frequency
of the CPU and all synchronous peripherals. clk
I/O, clkADC, clkCPU, and clkFLASH are divided by a
factor as shown in Table 7-11.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
7.10.1
Clock Prescaler Register – CLKPR
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bit
7
6543
2
1
0
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
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