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6437E–ATARM–23-Apr-13
SAM9M11
9.
ARM926EJ-S Processor Overview
9.1
Description
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose micropro-
cessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-
tasking applications where full memory management, high performance, low die size and low
power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets,
enabling the user to trade off between high performance and high code density. It also supports
8-bit Java instruction set and includes features for efficient execution of Java bytecode, provid-
ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-
powered wireless and embedded devices. It includes an enhanced multiplier design for
improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist
in both hardware and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
an ARM9EJ-S integer core
a Memory Management Unit (MMU)
separate instruction and data AMBA AHB bus interfaces
separate instruction and data TCM interfaces