參數(shù)資料
型號(hào): AT89LP51-20MU
廠商: Atmel
文件頁(yè)數(shù): 46/117頁(yè)
文件大?。?/td> 0K
描述: MCU 8051 4K FLASH 20MHZ 7X7MLF
標(biāo)準(zhǔn)包裝: 360
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤(pán)
包裝: 托盤(pán)
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34
3709D–MICRO–12/11
AT89LP51/52
The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that
ensures that the device is reset from system power up. In most cases a RC startup circuit is not
required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a
board-level reset is not present.
Note:
RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external
reset pin is held active. When ISP is disabled by fuse, ISP may only be entered by pulling RST
active during power-up. If this behavior is necessary, it is recommended to use an active-low reset
so that ISP can be entered by shorting RST to GND at power-up.
Figure 7-3.
Reset Pin Structure
7.4
Watchdog Reset
When the Watchdog times out, it will generate a reset pulse lasting 49 clock cycles. By default
this pulse is also output on the RST pin. To disable the RST output the DISRTO bit in AUXR
(Compatibility mode) or WDTCON (Fast mode) must be set to one. Watchdog reset will set the
WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence
1EH/E1H must be written to WDTRST before the Watchdog times out. See “Programmable
Watchdog Timer” on page 73. for details on the operation of the Watchdog.
7.5
Software Reset
The CPU may generate a 49-clock cycle reset pulse by writing the software reset sequence
5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTCON. See
“Software Reset” on page 73 for more information on software reset. Writing any sequences
other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both
WDTOVF and SWRST to flag an error. Software reset will also drive the RST pin active unless
DISRTO is set.
8.
Power Saving Modes
The AT89LP51/52 supports two different power-reducing modes: Idle and Power-down. These
modes are accessed through the PCON register. Additional steps may be required to achieve
the lowest possible power consumption while using these modes.
8.1
Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
VCC
DISRTO
WDT Reset
RST
Internal Reset
POL = 1
VCC
DISRTO
WDT Reset
RST
Internal Reset
POL = 0
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AT89LP51ED2-20AAU 功能描述:8位微控制器 -MCU 64KB 20MHz 2.4V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51ED2-20AU 功能描述:8位微控制器 -MCU 64KB 20MHz 2.4V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51ED2-20JU 功能描述:8位微控制器 -MCU 64KB 20MHz 2.4V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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