參數(shù)資料
型號： AT89C51IC2-SLRIM
廠商： Atmel
文件頁數(shù)： 126/140頁
文件大?。?/td> 0K
描述： IC MCU FLASH 8051 32K 5V 44-PLCC
標(biāo)準(zhǔn)包裝： 1
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 60MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 剪切帶 (CT)
其它名稱： AT89C51IC2SLRIMCT
86
AT89C51IC2
4301D–8051–02/08
Description
The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis-
ters: the Synchronous Serial Control register (SSCON; Table 73), the Synchronous
Serial Data register (SSDAT; Table 74), the Synchronous Serial Control and Status reg-
ister (SSCS; Table 75) and the Synchronous Serial Address register (SSADR Table 78).
SSCON is used to enable SSLC, to program the bit rate (see Table 66), to enable slave
modes, to acknowledge or not a received data, to send a START or a STOP condition
on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables
SSLC.
In write mode, SSCS is used to select the 2-wire interface and to select the bit rate
source. In read mode, SSCS contains a status code which reflects the status of the 2-
wire logic and the 2-wire bus. The three least significant bits are always zero. The five
most significant bits contains the status code. There are 26 possible status codes. When
SSCS contains F8h, no relevant state information is available and no serial interrupt is
requested. A valid status code is available in SSCS one machine cycle after SI is set by
hardware and is still present one machine cycle after SI has been reset by software.
Table 68.to Table 72. give the status for the master modes and miscellaneous states.
SSDAT contains a byte of serial data to be transmitted or a byte which has just been
received. It is addressable while it is not in process of shifting a byte. This occurs when
2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT
remains stable as long as SI is set. While data is being shifted out, data on the bus is
simultaneously shifted in; SSDAT always contains the last byte present on the bus.
SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which
SSLC will respond when programmed as a slave transmitter or receiver. The LSB is
used to enable general call address (00h) recognition.
Figure 37 shows how a data transfer is accomplished on the 2-wire bus.
Figure 37. Complete data transfer on 2-wire bus
The four operating modes are:
Master Transmitter
Master Receiver
Slave transmitter
Slave receiver
Data transfer in each mode of operation is shown in Table 68 to Table 72 and Figure 38.
to Figure 41.. These figures contain the following abbreviations:
S : START condition
SDA
SCL
S
start
condition
MSB
1
2
7
8
9
ACK
acknowledgement
signal from receiver
acknowledgement
signal from receiver
1
2
3-8
9
ACK
stop
condition
P
clock line held low
while interrupts are serviced
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AT89C51IC2-SLRUL 功能描述:8位微控制器 -MCU C51IC2 32K FLASH I2C 32KHz 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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AT89C51IC2-SLSCM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with 2-wire Interface
AT89C51IC2-SLSIL 功能描述:IC 8051 MCU FLASH 32K 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件
AT89C51IC2-SLSIM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with 2-wire Interface
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