參數(shù)資料
型號: AT89C51ED2-SLRUM
廠商: Atmel
文件頁數(shù): 100/137頁
文件大小: 0K
描述: IC MCU FLASH 8051 64K 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT89C51ED2-SLRUMDKR
65
4235K–8051–05/08
AT89C51RD2/ED2
16.3
Functional Description
Figure 16-2 shows a detailed structure of the SPI Module.
Figure 16-2. SPI Module Block Diagram
16.3.1
Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI Module is made through one register:
The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex trans-
mission with both data out and data in synchronized with the same clock (Figure 16-3).
Shift Register
0
1
2
3
4
5
6
7
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOL
MSTR
SSDIS
SPEN
SPR2
SPCON
WCOL
MODF
SPIF
-
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