
51
4431E–8051–04/06
AT/TS8xC54/8X2
Table 19-10. AC Parameters for a Variable Clock: derating formula
19.5.5
External Data Memory Write Cycle
Figure 19-7. External Data Memory Write Cycle
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TRLRH
Min
6 T - x
3 T - x
20
15
25
ns
TWLWH
Min
6 T - x
3 T - x
20
15
25
ns
TRLDV
Max
5 T - x
2.5 T - x
25
23
30
ns
TRHDX
Min
xx0
0
ns
T
RHDZ
Max
2 T - x
T - x
20
15
25
ns
TLLDV
Max
8 T - x
4T -x
40
35
45
ns
TAVDV
Max
9 T - x
4.5 T - x
60
50
65
ns
TLLWL
Min
3 T - x
1.5 T - x
25
20
30
ns
TLLWL
Max
3 T + x
1.5 T + x
25
20
30
ns
T
AVWL
Min
4 T - x
2 T - x
25
20
30
ns
TQVWX
Min
T - x
0.5 T - x
15
10
20
ns
TQVWH
Min
7 T - x
3.5 T - x
15
10
20
ns
TWHQX
Min
T - x
0.5 T - x
10
8
15
ns
T
RLAZ
Max
xx0
0
ns
T
WHLH
Min
T - x
0.5 T - x
15
10
20
ns
TWHLH
Max
T + x
0.5 T + x
15
10
20
ns
T
QVWH
T
LLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7
DATA OUT
ADDRESS
OR SFR-P2
T
AVWL
TLLWL
T
QVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
T
WLWH