TS80C52X2 is compatible with the timer 2 in the 80C52" />
參數(shù)資料
型號: AT87C52X2-SLSUL
廠商: Atmel
文件頁數(shù): 4/55頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K OTP 30MHZ 44PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 30/20MHz
連通性: UART/USART
外圍設(shè)備: POR
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
12
TS8xCx2X2
4184I–8051–02/08
Timer 2
The timer 2 in the
TS80C52X2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and
T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2
selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer
clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as
described in the Atmel 8-bit Microcontroller Hardware description.
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Cap-
ture and Baud Rate Generator Modes.
In
TS80C52X2 Timer 2 includes the following enhancements:
Auto-reload mode with up or down counter
Programmable clock-output
Auto-reload Mode
The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-
matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an
Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direc-
tion of the count. EXF2 does not generate any interrupt. This bit can be used to provide
17-bit resolution.
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