
1
2153BS–BDC–08/03
Features
Dual ADC
8-bit Resolution
1 Gsps Sampling Rate Per Channel
2 Gsps Equivalent Sampling Rate With One Channel (Interlaced Mode)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50
PECL/LVDS Compatible Clock Inputs
LVDS Output Format (100
)
3-wire Serial Interface (16-bit Data, 3-bit Address):
– Full or Partial Standby Mode
– 1:2 or 1:1 Selectable Data Output Demultiplexer
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Asynchronous Data Ready Reset
– Data Ready Delay Adjustable On Both Channels
– Interlacing Functions:
Offset And Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) On One Channel
Internal Static Or Dynamic Built-in Test (BIT)
Very Low Input Capacitance: 2 pF
Power Supply: 3.3 V (Analog), 3.3 V (Digital), 2.25 V (Output)
LQFP144
Temperature Range:
– “C” Grade: 0°C < T
A
< 70°C
– “I” Grade: -20°C < T
A
< 85°C
Performance
Low Power Consumption: 1.4 W (Typ)
Power Consumption in Standby Mode: 60 mW
1.5 GHz Full Power Input Bandwidth (-3 dB)
SINAD = 46 dB Typ (7.3 ENOB), THD = -60 db, SFDR = - 62 dB
at Fs = 1 Gsps, Fin = 500 MHz
2-tone IMD: -60 dBc Min (499 MHz, 501 MHz) at 1 Gsps
DNL = 0.25 LSB Typ, INL = 0.5 LSB Typ
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
Low Bit Error Rate (2.10
-13
) at 1 Gsps
Application
Instrumentation
Satellite Receiver
Direct RF Down Conversion
WLAN
Description
The AD84AD001B is a monolithic low-power (1.4 W typ) dual 8-bit analog-to-digital converter,
designed for digitizing in-phase (I) and quadrature (Q) wide bandwidth analog signals at very high
sampling rates of up to 1 Gsps. The ability to directly interface I and Q signals makes the
AD84AD001B ideal for use in direct satellite demodulation applications or dual channel acquisition
applications (instrumentation).
The AD84AD001B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and
is manufactured with an advanced high-speed BiCMOS process.
The on-chip 2 S/H have a well matched 1.5 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (high IF digitizing).
A 3-wire serial bus interface provides extra adjustment (standby mode, input range, Gray or binary
coding).
Dual 8-bit
1 Gsps ADC
AT84AD001B
Smart ADC
Preliminary
Summary
For more information
please contact
hotline-bdc@gfo.atmel.com