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參數資料
| 型號： | AT80C51RA2-SLSUM |
| 廠商： | International Rectifier |
| 英文描述： | High Performance 8-bit Microcontroller |
| 中文描述： | 高性能8位微控制器 |
| 文件頁數： | 46/85頁 |
| 文件大?。?/td> | 762K |
| 代理商： | AT80C51RA2-SLSUM |
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46
4188E–8051–08/06
AT/TS8xC51Rx2
6.8
Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
6.8.1
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
OSC
, where T
OSC
=
1/F
OSC
. To make the best use of the WDT, it should be serviced in those sections of code that
will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
7
counter has been added to extend the Time-out capability,
ranking from 16ms to 2s @ F
OSC
= 12MHz. To manage this feature, refer to WDTPRG register
description,
Table 6-22
(SFR0A7h).
Table 6-21.
WDTRST Register
WDTRST Address (0A6h)
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
Table 6-22.
WDTPRG Register
WDTPRG Address (0A7h)
6
7
6
5
4
3
2
1
Reset value
X
X
X
X
X
X
X
7
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
相關PDF資料 |
PDF描述 |
|---|---|
| AT80C51RD2-3CSUL | High Performance 8-bit Microcontroller |
| AT80C51RD2-3CSUM | High Performance 8-bit Microcontroller |
| AT80C51RD2-RLTUL | High Performance 8-bit Microcontroller |
| AT80C51RD2-RLTUM | High Performance 8-bit Microcontroller |
| AT80C51RD2-SLSUL | High Performance 8-bit Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AT80C51RB2-3CSCM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-3CSIM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-3CSUM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
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