參數(shù)資料
型號: AT80C51-25R
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù): 96/170頁
文件大?。?/td> 4133K
代理商: AT80C51-25R
31
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
8.3.1
Procedure for Changing the Watchdog Timer Configuration
The sequence for changing configuration differs between the two safety levels, as follows:
8.3.1.1
Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any
restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled
Watchdog Timer, the following procedure must be followed:
1.
Write the signature for change enable of protected I/O registers to register CCP
2.
Within four instruction cycles, in the same operation, write WDE and WDP bits
8.3.1.2
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A protected change
is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following proce-
dure must be followed:
1.
Write the signature for change enable of protected I/O registers to register CCP
2.
Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
8.3.2
Code Examples
The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled
(e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Note:
Table 8-1.
WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT
Initial State
How to
Disable the WDT
How to
Change Time-out
Unprogrammed
1
Disabled
Protected change
sequence
No limitations
Programmed
2
Enabled
Always enabled
Protected change
sequence
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in
r16, RSTFLR
andi
r16, ~(1<<WDRF)
out
RSTFLR, r16
; Write signature for change enable of protected I/O register
ldi
r16, 0xD8
out
CCP, r16
; Within four instruction cycles, turn off WDT
ldi
r16, (0<<WDE)
out
WDTCSR, r16
ret
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