IH
參數(shù)資料
型號(hào)： AT6010A-4AC
廠商： Atmel
文件頁數(shù)： 11/28頁
文件大?。?/td> 0K
描述： IC FPGA 4NS 144TQFP
標(biāo)準(zhǔn)包裝： 90
系列： AT6000(LV)
邏輯元件/單元數(shù)： 6400
輸入/輸出數(shù)： 120
門數(shù)： 30000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 144-TQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： AT6010A4AC
AT6000(LV) Series
19
AC Timing Characteristics – 5V Operation
Notes:
1. TTL buffer delays are measured from a V
IH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.
2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the apd to the internal VIH at A. The input buffer load is constant.
3. Buffer delay is to a pad voltage of 1.5V with one output switching.
4. Max specifications are the average of mas t
PDLH and tPDHL.
5. Parameter based on characterization and simulation; not tested in production
6. Exact power calculation is available in an Atmel application note.
7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF.
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: V
CC = 4.75V to 5.25V. Temperature = 0°C to 70°C.
Cell Function
Parameter
From
To
Load
Definition
-1
-2
-4
Units
Wire
t
PD (max)
A, B, L
A, B
1
0.8
1.2
1.8
ns
NAND
t
PD (max)
A, B, L
B
1
1.6
2.2
3.2
ns
XOR
tPD (max)
A, B, L
A
1
1.8
2.4
4.0
ns
AND
t
PD (max)
A, B, L
B
1
1.7
2.2
3.2
ns
MUX
tPD (max)
A, B
A
1
1.7
2.3
4.0
ns
LA
1
2.1
3.0
4.9
ns
D-Flip-flop
t
setup (min)
A, B, L
CLK
-
1.5
2.0
3.0
ns
D-Flip-flop
t
hold (min)
CLK
A, B, L
-
000
ns
D-Flip-flop
tPD (max)
CLK
A
1
1.5
2.0
3.0
ns
Bus Driver
t
PD (max)
A
L
2
2.0
2.6
4.0
ns
Repeater
tPD (max)
L, E
E
3
1.3
1.6
2.3
ns
L, E
L
2
1.7
2.1
3.0
ns
Column Clock
t
PD (max)
GCLK, A, ES
CLK
3
1.8
2.4
3.0
ns
Column Reset
t
PD (max)
GRES, A, EN
RES
3
1.8
2.4
3.0
ns
Clock Buffer
tPD (max)
CLOCK PIN
GCLK
-
1.6
2.0
2.9
ns
Reset Buffer
t
PD (max)
RESET PIN
GRES
-
1.5
1.9
2.8
ns
TTL Input
t
PD (max)
I/O
A
3
1.0
1.2
1.5
ns
CMOS Input
tPD (max)
I/O
A
3
1.3
1.4
2.3
ns
Fast Output
t
PD (max)
A
I/O PIN
4
3.3
3.5
6.0
ns
Slow Output
t
PD (max)
A
I/O PIN
4
7.5
8.0
12.0
ns
Output Disable
tPXZ (max)
L
I/O PIN
4
3.1
3.3
5.5
ns
Fast Enable
t
PXZ (max)
L
I/O PIN
4
3.8
4.0
6.5
ns
Slow Enable
t
PXZ (max)
L
I/O PIN
4
8.2
8.5
12.5
ns
Device
Cell Types
Outputs
ICC (max)
Cell
Wire, XWire, Half-adder, Flip-flop
A, B
4.5 A/MHz
Bus
Wire, XWire, Half-adder, Flip-flop, Repeater
L
2.5 A/MHz
Column Clock
Column Clock Driver
CLK
40 A/MHz
= Preliminary Information
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AT6010A-4AI 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA 30K GATE 4NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6010A-4QC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
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