參數資料
| 型號： | AT6010-2QI |
| 廠商： | Atmel |
| 文件頁數： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2NS 132BQFP |
| 標準包裝： | 36 |
| 系列： | AT6000(LV) |
| 邏輯元件/單元數： | 6400 |
| 輸入/輸出數： | 108 |
| 門數： | 30000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應商設備封裝： | 132-BQFP |
| 其它名稱： | AT60102QI |
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AT6000(LV) Series
5
In addition to the four local-bus connections, a cell receives
two inputs and p rovides two outputs to ea ch of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B”. There is an A input and a B input from each neigh-
boring cell and an A output and a B output driving all four
neighbors. Between cells, an A output is always connected
to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers. Cell
flexibility is enhanced by allowing each multiplexer to select
also the logical constant “1”. The two multiplexer outputs
enter the two upstream AND gates.
Downstream from these two AND gates are an Exclusive-
OR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the
A and B input multiplexers) and determine the function of
the cell.
In State 0 – corresponding to the “0” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output of
the right-hand upstream AND gate is connected to the
cell’s B output.
In State 1 – corresponding to the “1” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
In State 2 – corresponding to the “2” inputs of the
multiplexers – the XOR of the outputs from the two
upstream AND gates is provided to the cell’s A output,
while the NAND of these two outputs is provided to the
cell’s B output.
In State 3 – corresponding to the “3” inputs of the
multiplexers – the XOR function of State 2 is provided to
the D input of a D-type flip-flop, the Q output of which is
connected to the cell’s A output. Clock and
asynchronous reset signals are supplied externally as
described later. The AND of the outputs from the two
upstream AND gates is provided to the cell's B output.
Logic States
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logical cell states which per-
mutate into 72 physical states. Some states use both A and
B inputs. Other states are created by selecting the “1” input
on either or both of the input multiplexers.
There are 28 combinatorial primitives created from the
cell’s tristate capabilities and the 20 physical states repre-
sented in Figure 5. Five logical primitives are derived from
the physical constants shown in Figure 7. More complex
functions are created by using cells in combination.
A two-input AND feeding an XOR (Figure 8) is produced
using a single cell (Figure 9). A two-to-one multiplexer
selects the logical constant “0” and feeds it to the right-
hand AND gate. The AND gate acts as a feed-through, let-
ting the B input pass through to the XOR. The three-to-one
multiplexer on the right side selects the local-bus input,
LNS1, and passes it to the left-hand AND gate. The A and
LNS1 signals are the inputs to the AND gate. The output of
the AND gate feeds into the XOR, producing the logic state
(AlL) XOR B.
相關PDF資料 |
PDF描述 |
|---|---|
| AT6010-2QC | IC FPGA 2NS 132BQFP |
| AT6005A-4AI | IC FPGA 15K GATE 4NS 144TQFP |
| AT6005A-4AC | IC FPGA 15K GATE 4NS 144TQFP |
| AT6005A-2AI | IC FPGA 2NS 144TQFP |
| AT6005A-2AC | IC FPGA 15K GATE 2NS 144TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AT6010-2UC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| AT6010-4JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6010-4JI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6010-4QC | 功能描述:FPGA - 現場可編程門陣列 30K GATE 4NS COM TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6010-4QI | 功能描述:FPGA - 現場可編程門陣列 30K GATE 4NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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