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參數(shù)資料
| 型號： | AT6005-4QI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 15K GATE 4NS 132BQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | AT6000(LV) |
| 邏輯元件/單元數(shù)： | 3136 |
| 輸入/輸出數(shù)： | 108 |
| 門數(shù)： | 15000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應(yīng)商設(shè)備封裝： | 132-BQFP |
| 其它名稱： | AT60054QI |
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AT6000(LV) Series
8
Figure 11. A-type I/O Logic
Figure 12. B-type I/O Logic
TTL/CMOS Inputs
A user-configurable bit determines the threshold level –
TTL or CMOS – of the input buffer.
Open Collector/Tristate Outputs
A user-configurable bit which enables or disables the active
pull-up of the output device.
Slew Rate Control
A user-configurable bit controls the slew rate – fast or slow
– of the output buffer. A slow slew rate, which reduces
noise and ground bounce, is recommended for outputs that
are not speed-critical. Fast and slow slew rates have the
same DC-current sinking capabilities, but the rate at which
each allows the output devices to reach full drive differs.
Pull-up
A user-configurable bit controls the pull-up transistor in the
I/O pin. It’s primary function is to provide a logical “1” to
unused input pins. When on, it is approximately equivalent
to a 25K resistor to V
CC.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static – always on or
always off – or dynamically controlled by a signal gener-
ated in the array. Four options are available from the array:
(1) the control is low and always driving; (2) the control is
high and never driving; (3) the control is connected to a ver-
tical local bus associated with the output cell; or (4) the
control is connected to a horizontal local bus associated
with the output cell. On power-up, the user I/Os are config-
ured as inputs with pull-up resistors.
In addition to the functionality provided by the I/O logic, the
entrance and exit cells provide the ability to register both
inputs and outputs. Also, these perimeter cells (unlike inte-
rior cells) are connected directly to express buses: the
edge-facing A and B outputs of the entrance cell are con-
nected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to the
edge, and provide a rapid means of bringing I/O signals to
and from the array interior and the opposite edge of the
chip.
Chip Configuration
The Integrated Development System generates the SRAM
bit pattern required to configure a AT6000 Series device. A
PC parallel port, microprocessor, EPROM or serial configu-
ration memory can be used to download configuration
patterns.
Users select from several configuration modes. Many fac-
tors, including board area, configuration speed and the
number of designs implemented in parallel can influence
the user’s final choice.
Configuration is controlled by dedicated configuration pins
and dual-function pins that double as I/O pins when the
device is in operation. The number of dual-function pins
required for each mode varies.
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| IDT71V016SA20BFG | IC SRAM 1MBIT 20NS 48FBGA |
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| HMC65DREI | CONN EDGECARD 130POS .100 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT6005-4UC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| AT6005-4UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| AT6005A-2AC | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15K GATE - 2NS 144 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6005A-2AI | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA 15K GATE 2NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6005A-2QC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
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