參數(shù)資料
型號(hào)： AT6003-2JI
廠商： Atmel
文件頁(yè)數(shù)： 28/28頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2NS 84PLCC
標(biāo)準(zhǔn)包裝： 16
系列： AT6000(LV)
邏輯元件/單元數(shù)： 1600
輸入/輸出數(shù)： 64
門數(shù)： 9000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.31x29.31）
其它名稱： AT60032JI
AT6000(LV) Series
9
The devices can be partially reconfigured while in opera-
tion. Portions of the device not being modified remain
operational during reconfiguration. Simultaneous configu-
ration of more than one device is also possible. Full
configuration takes as little as a millisecond, partial configu-
ration is even faster.
Refer to the Pin Function Description section following for a
brief summary of the pins used in configuration. For more
information about configuration, refer to the AT6000 Series
Configuration data sheet.
Pin Function Description
This section provides abbreviated descriptions of the vari-
ous AT6000 Series pins. For more complete descriptions,
refer to the AT6000 Series Configuration data sheet.
Pinout tables for the AT6000 series of devices follow.
Power Pins
V
CC, VDD, GND, VSS
V
CC and GND are the I/O supply pins, VDD and VSS are the
internal logic supply pins. V
CC and VDD should be tied to the
same trace on the printed circuit board. GND and V
SS
should be tied to the same trace on the printed circuit
board.
Input/Output Pins
All I/O pins can be used in the same way (refer to the I/O
section of the architecture description). Some I/O pins are
dual-function pins used during configuration of the array.
When not being used for configuration, dual-function I/Os
are fully functional as normal I/O pins. On initial power-up,
all I/Os are configured as TTL inputs with a pull-up.
Dedicated Timing and Control Pins
CON
Configuration-in-process pin. After power-up, CON stay-
sLow until power-up initialization is complete, at which time
CON is then released. CON is an open collector signal.
After power-up initialization, forcing CON low begins the
configuration process.
CS
Configuration enable pin. All configuration pins are ignored
if CS is high. CS must be held low throughout the configu-
ration process. CS is a TTL input pin.
M0, M1, M2
Configuration mode pins are used to determine the config-
uration mode. All three are TTL input pins.
CCLK
Configuration clock pin. CCLK is a TTL input or a CMOS
output depending on the mode of operation. In modes 1, 2,
3, and 6 it is an input. In modes 4 and 5 it is an output with
a typical frequency of 1 MHz. In all modes, the rising edge
of the CCLK signal is used to sample inputs and change
outputs.
CLOCK
External logic source used to drive the internal global clock
line. Registers toggle on the rising edge of CLOCK. The
CLOCK signal is neither used nor affected by the configu-
ration modes. It is always a TTL input.
RESET
Array register asynchronous reset. RESET drives the inter-
nal global reset. The RESET signal is neither used nor
affected by the configuration modes. It is always a TTL
input.
Dual-function Pins
When CON is high, dual-function I/O pins act as device
I/Os; when CON is low, dual-function pins are used as con-
figuration control or data signals as determined by the
configuration modes. Care must be taken when using
these pins to ensure that configuration activity does not
interfere with other circuitry connected to these pins in the
application.
D0 or I/O
Serial configuration modes use D0 as the serial data input
pin. Parallel configuration modes use D0 as the least-sig-
ni fic a n t bi t. Inpu t d a ta mus t mee t s e tu p a nd hol d
requirements with respect to the rising edge of CCLK. D0 is
a TTL input during configuration.
D1 to D7 or I/O
Parallel configuration modes use these pins as inputs.
Serial configuration modes do not use them. Data must
meet setup and hold requirements with respect to the rising
edge of CCLK. D1 - D7 are TTL inputs during configuration.
A0 to A16 or I/O
During configuration in modes 1, 2 and 5, these pins are
CMOS outputs and act as the address pins for a parallel
EPROM. A0 - A16 eliminates the need for an external
address counter when using an external parallel nonvolatile
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT6003-2QC 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-2QI 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4AC 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 9K GATE 4NS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4AI 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 AT6K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4JC 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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