參數(shù)資料
型號(hào)： AT6002-4AC
廠商： Atmel
文件頁(yè)數(shù)： 24/28頁(yè)
文件大小： 0K
描述： IC FPGA 6K GATE 4NS 100VQFP
標(biāo)準(zhǔn)包裝： 90
系列： AT6000(LV)
邏輯元件/單元數(shù)： 1024
輸入/輸出數(shù)： 80
門(mén)數(shù)： 6000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
其它名稱： AT60024AC
AT6000(LV) Series
5
In addition to the four local-bus connections, a cell receives
two inputs and p rovides two outputs to ea ch of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B”. There is an A input and a B input from each neigh-
boring cell and an A output and a B output driving all four
neighbors. Between cells, an A output is always connected
to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers. Cell
flexibility is enhanced by allowing each multiplexer to select
also the logical constant “1”. The two multiplexer outputs
enter the two upstream AND gates.
Downstream from these two AND gates are an Exclusive-
OR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the
A and B input multiplexers) and determine the function of
the cell.
In State 0 – corresponding to the “0” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output of
the right-hand upstream AND gate is connected to the
cell’s B output.
In State 1 – corresponding to the “1” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
In State 2 – corresponding to the “2” inputs of the
multiplexers – the XOR of the outputs from the two
upstream AND gates is provided to the cell’s A output,
while the NAND of these two outputs is provided to the
cell’s B output.
In State 3 – corresponding to the “3” inputs of the
multiplexers – the XOR function of State 2 is provided to
the D input of a D-type flip-flop, the Q output of which is
connected to the cell’s A output. Clock and
asynchronous reset signals are supplied externally as
described later. The AND of the outputs from the two
upstream AND gates is provided to the cell's B output.
Logic States
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logical cell states which per-
mutate into 72 physical states. Some states use both A and
B inputs. Other states are created by selecting the “1” input
on either or both of the input multiplexers.
There are 28 combinatorial primitives created from the
cell’s tristate capabilities and the 20 physical states repre-
sented in Figure 5. Five logical primitives are derived from
the physical constants shown in Figure 7. More complex
functions are created by using cells in combination.
A two-input AND feeding an XOR (Figure 8) is produced
using a single cell (Figure 9). A two-to-one multiplexer
selects the logical constant “0” and feeds it to the right-
hand AND gate. The AND gate acts as a feed-through, let-
ting the B input pass through to the XOR. The three-to-one
multiplexer on the right side selects the local-bus input,
LNS1, and passes it to the left-hand AND gate. The A and
LNS1 signals are the inputs to the AND gate. The output of
the AND gate feeds into the XOR, producing the logic state
(AlL) XOR B.
相關(guān)PDF資料
PDF描述
AT6002-2QI IC FPGA 2NS 132BQFP
AT6002-2QC IC FPGA 6K GATE 2NS 132BQFP
AMM31DTKI CONN EDGECARD 62POS DIP .156 SLD
AT6002-2JI IC FPGA 2NS 84PLCC
AT6002-2JC IC FPGA 6K GATE 2NS 84PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT6002-4AI 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 6K GATE 4NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6002-4JC 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 6K GATE 4NS 84 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6002-4JI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6002-4QC 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6002-4QI 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*