參數(shù)資料
型號: AT43312A-SC
廠商: ATMEL CORP
元件分類: 總線控制器
英文描述: Self- and Bus-Bus-powered USB Hub Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO32
封裝: 0.440 INCH, PLASTIC, SOIC-32
文件頁數(shù): 5/28頁
文件大?。?/td> 211K
代理商: AT43312A-SC
5
AT43312A
1255G–USB–05/06
Signal Description
OSC1
Oscillator Input. Input to the inverting 6 MHz oscillator amplifier.
OSC2
Oscillator Output. Output of the inverting oscillator amplifier.
LFT
PLL Filter. For proper operation of the PLL, this pin should be connected through a
2.2 nF capacitor in parallel with a 100
resistor in series with a 10 nF capacitor to
ground (VSS).
SELF/BUS
Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high
on this pin enables the self-powered mode, a low enables the bus-powered mode.
LPSTAT
Local Power Status. In the self-powered mode, this is an input pin that should be con-
nected to the local power supply through a 47 k
resistor. The voltage on this pin is
used by the chip for reporting the condition of the local power supply. In the bus-pow-
ered mode, this pin is not used.
DP0
Upstream Plus USB I/O. This pin should be connected to CEXT through an external
1.5 k
pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to
the Host Controller or an upstream Hub.
DM0
Upstream Minus USB I/O.
DP[1:4]
Port Plus USB I/O. This pin should be connected to VSS through an external 15 k
resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream
USB devices.
DM[1:4]
Port Minus USB I/O. This pin should be connected to VSS through an external 15 k
resistor
OVC[1:4]
Overcurrent. This is the input signal used to indicate to the AT43312A that an overcur-
rent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and
report the status to the USB Host.
PWR[1:4]
Power Switch. This is an output signal used to enable or disable the external voltage
regulator supplying power to a port. PWRx is de-asserted when a power supply problem
is detected at OVCx.
STAT[1:4]
Connect Status. This is an output pin indicating that a port is properly connected. STATx
is asserted when the port is enabled.
CEXT
External Capacitor. For proper operation of the on chip regulator, a 0.27 μF capacitor
must be connected to this pin.
TEST
Test. This pin should be connected to a logic high for normal operation.
VCC
5V Power Supply.
VSS
Ground.
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