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參數(shù)資料
| 型號(hào)： | AT40K40AL |
| 廠商： | Atmel Corp. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | 5K - 50K Gates Coprocessor FPGA with FreeRAM |
| 中文描述： | 5K - 50K的蓋茨與FreeRAM的FPGA協(xié)處理器 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 43K |
| 代理商： | AT40K40AL |
3
AT40KAL Series FPGA
2818ES–FPGA–1/04
Cache Logic Design
The AT40KAL, AT6000 and FPSLIC families are capable of implementing Cache Logic
(dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building
adaptive logic and systems. As new logic functions are required, they can be loaded into
the logic cache without losing the data already there or disrupting the operation of the
rest of the chip; replacing or complementing the active logic. The AT40KAL can act as a
reconfigurable coprocessor.
Automatic Component
Generators
The AT40KAL FPGA family is capable of implementing user-defined, automatically gen-
erated, macros in multiple designs; speed and functionality are unaffected by the macro
orientation or density of the target device. This enables the fastest, most predictable and
efficient FPGA design approach and minimizes design risk by reusing already proven
functions. The Automatic Component Generators work seamlessly with industry stan-
dard schematic and synthesis tools to create the fastest, most efficient designs
available.
The patented AT40KAL series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable I/O.
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to
3,048 registers. Pin locations are consistent throughout the AT40KAL series for easy
design migration in the same package footprint. The AT40KAL series FPGAs utilize a
reliable 0.35μ triple-metal, CMOS process and are 100% factory-tested. Atmel’s PC-
and workstation-based integrated development system (IDS) is used to create
AT40KAL series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
For a complete version of this datasheet, refer to the FPGA section of the Atmel web
site, www.atmel.com.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT40K40AL-1BGC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA |
| AT40K40AL-1BGI | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA |
| AT40K40AL-1BQC | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA 40K GATE 3.3V 1NS COM TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT40K40AL-1BQI | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA 40K GATE 3.3V 1NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT40K40AL-1BQU | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3.3V 1ns RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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