參數(shù)資料
型號(hào): AT32UC3L064-D3UR
廠商: Atmel
文件頁數(shù): 151/174頁
文件大?。?/td> 0K
描述: MCU AVR32 64KB FLASH 48TLLGA
標(biāo)準(zhǔn)包裝: 8,000
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-UFLGA
包裝: 帶卷 (TR)
其它名稱: 32UC3L064-D3UR
32UC3L064-D3UR-ND
78
32099I–01/2012
AT32UC3L016/32/64
8.3.4
Debug Operation
When an external debugger forces the CPU into debug mode, the FLASHCDW continues nor-
mal operation. If the FLASHCDW is configured in a way that requires it to be periodically
serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
8.4
Functional Description
8.4.1
Bus Interfaces
The FLASHCDW has two bus interfaces, one High Speed Bus (HSB) interface for reads from the
flash memory and writes to the page buffer, and one Peripheral Bus (PB) interface for issuing
commands and reading status from the controller.
8.4.2
Memory Organization
The flash memory is divided into a set of pages. A page is the basic unit addressed when pro-
gramming the flash. A page consists of several words. The pages are grouped into 16 regions of
equal size. Each of these regions can be locked by a dedicated fuse bit, protecting it from acci-
dental modification.
p pages (FLASH_P)
w bytes in each page and in the page buffer (FLASH_W)
pw bytes in total (FLASH_PW)
f general-purpose fuse bits (FLASH_F), used as region lock bits and for other device-specific
purposes
1 security fuse bit
1 User page
8.4.3
User Page
The User page is an additional page, outside the regular flash array, that can be used to store
various data, such as calibration data and serial numbers. This page is not erased by regular
chip erase. The User page can only be written and erased by a special set of commands. Read
accesses to the User page are performed just as any other read accesses to the flash. The
address map of the User page is given in Figure 8-1 on page 80.
8.4.4
Read Operations
The on-chip flash memory is typically used for storing instructions to be executed by the CPU.
The CPU will address instructions using the HSB bus, and the FLASHCDW will access the flash
memory and return the addressed 32-bit word.
In systems where the HSB clock period is slower than the access time of the flash memory, the
FLASHCDW can operate in 0 wait state mode, and output one 32-bit word on the bus per clock
cycle. If the clock frequency allows, the user should use 0 wait state mode, because this gives
the highest performance as no stall cycles are encountered.
The FLASHCDW can also operate in systems where the HSB bus clock period is faster than the
access speed of the flash memory. Wait state support and a read granularity of 64 bits ensure
efficiency in such systems.
Performance for systems with high clock frequency is increased since the internal read word
width of the flash memory is 64 bits. When a 32-bit word is to be addressed, the word itself and
相關(guān)PDF資料
PDF描述
516-020-000-102 CONN PLUG 20POS RACK & PANEL
AT32UC3L032-D3UR MCU AVR32 32KB FLASH 48TLLGA
516-090-000-302 CONN RACK & PANEL PLUG 90POS
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