參數(shù)資料
型號: AT32UC3C264C-A2UR
廠商: Atmel
文件頁數(shù): 92/110頁
文件大?。?/td> 0K
描述: IC MCU AVR32 64K FLASH 64TQFP
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT32UC3C264C-A2URDKR
82
32117DS–AVR-01/12
AT32UC3C
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “nwe hold
length”
Table 7-54.
SMC Read Signals with no Hold Settings(1)
Symbol
Parameter
Conditions
Min
Units
NRD Controlled (READ_MODE = 1)
SMC
19
Data setup before NRD high
V
VDD = 3.0V,
drive strength of the pads set to the lowest,
external capacitor = 40pF
32.5
ns
SMC20
Data hold after NRD high
0
NRD Controlled (READ_MODE = 0)
SMC
21
Data setup before NCS high
V
VDD = 3.0V,
drive strength of the pads set to the lowest,
external capacitor = 40pF
28.5
ns
SMC22
Data hold after NCS high
0
Table 7-55.
SMC Write Signals with Hold Settings(1)
Symbol
Parameter
Conditions
Min
Units
NRD Controlled (READ_MODE = 1)
SMC23
Data Out valid before NWE high
V
VDD = 3.0V,
drive strength of the pads set
to the lowest,
external capacitor = 40pF
(nwe pulse length - 1) * tCPSMC - 1.4
ns
SMC
24
Data Out valid after NWE high(2)
nwe pulse length * tCPSMC - 4.7
SMC25
NWE high to NBS0/A0 change(2)
nwe pulse length * tCPSMC - 2.7
SMC
29
NWE high to NBS2/A1 change(2)
nwe pulse length * tCPSMC - 0.7
SMC
31
NWE high to A2 - A25 change(2)
nwe pulse length * tCPSMC - 6.8
SMC
32
NWE high to NCS inactive(2)
(nwe hold pulse - ncs wr hold length) *
tCPSMC - 2.5
SMC
33
NWE pulse width
nwe pulse length * tCPSMC - 0.2
NRD Controlled (READ_MODE = 0)
SMC
34
Data Out valid before NCS high
VVDD = 3.0V,
drive strength of the pads set
to the lowest,
external capacitor = 40pF
(ncs wr pulse length - 1) * tCPSMC - 2.2
ns
SMC
35
Data Out valid after NCS high(2)
ncs wr hold length * tCPSMC - 5.1
SMC
36
NCS high to NWE inactive(2)
(ncs wr hold length - nwe hold length) *
tCPSMC - 2
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