參數(shù)資料
型號: AT32UC3C2512C-Z2ZR
廠商: Atmel
文件頁數(shù): 35/109頁
文件大?。?/td> 0K
描述: IC MCU AVR32 512K FLASH 64QFN
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 標準包裝
其它名稱: AT32UC3C2512C-Z2ZRDKR
31
9166DS–AVR-01/12
AT32UC3C
Figure 4-5.
The Status Register Low Halfword
4.4.3
Processor States
4.4.3.1
Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
4.4.3.2
Debug State
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Bit 15
Bit 0
Reserved
Carry
Zero
Sign
0
-
T
-
Bit name
Initial value
0
L
Q
V
N
Z
C
-
Overflow
Saturation
-
Lock
Reserved
Scratch
Table 4-2.
Overview of Execution Modes, their Priorities and Privilege Levels.
Priority
Mode
Security
Description
1
Non Maskable Interrupt
Privileged
Non Maskable high priority interrupt mode
2
Exception
Privileged
Execute exceptions
3
Interrupt 3
Privileged
General purpose interrupt mode
4
Interrupt 2
Privileged
General purpose interrupt mode
5
Interrupt 1
Privileged
General purpose interrupt mode
6
Interrupt 0
Privileged
General purpose interrupt mode
N/A
Supervisor
Privileged
Runs supervisor calls
N/A
Application
Unprivileged
Normal program execution mode
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