參數(shù)資料
型號(hào): AT32UC3C0512C-ALZT
廠商: Atmel
文件頁(yè)數(shù): 33/109頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 300
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 123
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤(pán)
3
9166DS–AVR-01/12
AT32UC3C
1.
Description
The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC
processor running at frequencies up to 50 MHz. AVR32UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. Using the
Secure Access Unit (SAU) together with the MPU provides the required security and integrity.
Higher computation capabilities are achievable either using a rich set of DSP instructions or
using the floating-point instructions.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3C0 derivatives.
The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from
memories to memories without processor involvement.
The Peripheral Direct Memory Access (PDCA) controller enables data transfers between periph-
erals and memories without processor involvement. The PDCA drastically reduces processing
overhead when transferring continuous and large data streams.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
The FlashVault technology allows secure libraries to be programmed into the device. The secure
libraries can be executed while the CPU is in Secure State, but not read by non-secure software
in the device. The device can thus be shipped to end custumers, who are able to program their
own code into the device, accessing the secure libraries, without any risk of compromising the
proprietary secure code.
The Power Manager improves design flexibility and security. Power monitoring is supported by
on-chip Power-On Reset (POR), Brown-Out Detectors (BOD18, BOD33, BOD50). The CPU
runs from the on-chip RC oscillators, the PLLs, or the Multipurpose Oscillators. The Asynchro-
nous Timer (AST) combined with the 32 KHz oscillator keeps track of the time. The AST can
operate in counter or calendar mode.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The PWM module provides four channels with many configuration options including polarity,
edge alignment and waveform non overlap control. The PWM channels can operate indepen-
dently, with duty cycles set independently from each other, or in interlinked mode, with multiple
channels updated at the same time. It also includes safety feature with fault inputs and the ability
to lock the PWM configuration registers and the PWM pin assignment.
The AT32UC3C also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible CAN, USB and Ethernet MAC are available. The USART supports different communica-
tion modes, like SPI mode and LIN mode.
The Inter-IC Sound Controller (I2SC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with off-chip audio devices. The controller is compliant with the I2S bus specification.
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