參數(shù)資料
型號(hào): AT32UC3C0512C-ALZR
廠商: Atmel
文件頁(yè)數(shù): 4/109頁(yè)
文件大?。?/td> 0K
描述: IC MCU AVR32 512K FLASH 144LQFP
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 800
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 123
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤
101
9166DS–AVR-01/12
AT32UC3C
2
Requesting clocks in idle sleep modes will mask all other PB clocks than the
requested
In idle or frozen sleep mode, all the PB clocks will be frozen if the TWIS or the AST need to
wake the cpu up.
Fix/Workaround
Disable the TWIS or the AST before entering idle or frozen sleep mode.
3
TWIS may not wake the device from sleep mode
If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-
tion, the CPU may not wake upon a TWIS address match. The request is NACKed.
Fix/Workaround
When using the TWI address match to wake the device from sleep, do not switch to sleep
modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the
TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus
events.
10.2.6
SCIF
1
PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
2
PLL lock might not clear after disable
Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator
may not go back to zero after the PLL oscillator has been disabled. This can cause the prop-
agation of clock signals with the wrong frequency to parts of the system that use the PLL
clock.
Fix/Workaround
PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL
has been turned off, a delay of 30us must be observed after the PLL has been enabled
again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is
locked.
3
BOD33 reset locks the device
If BOD33 is enabled as a reset source (SCIF.BOD33.CTRL=0x1) and when VDDIN_33
power supply voltage falls below the BOD33 voltage (SCIF.BOD33.LEVEL), the device is
locked permanently under reset even if the power supply goes back above BOD33 reset
level. In order to unlock the device, an external reset event should be applied on RESET_N.
Fix/Workaround
Use an external BOD on VDDIN_33 or an external reset source.
10.2.7
SPI
1
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
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