參數(shù)資料
型號: AT32UC3A4128-C1UR
廠商: Atmel
文件頁數(shù): 74/94頁
文件大小: 0K
描述: IC MCU 128K FLASH 100VFBGA
產(chǎn)品培訓模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 A4
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB OTG
外圍設備: 欠壓檢測/復位,DMA,POR,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-VFBGA
包裝: 標準包裝
其它名稱: AT32UC3A4128-C1URDKR
76
32072SH–AVR32–10/2012
AT32UC3A3
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
10.1.8
Power Manager
OSC32
not
functionnal
in
Crystal
Modes
(OSC32CTRL.MODE=1
or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
10.1.9
PDCA
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
相關PDF資料
PDF描述
90327-0310 CONN RECEPT IDT 10POS 1.27MM TIN
90327-3306 CONN RECEPT IDT 6POS 1.27MM GOLD
90327-0308 CONN RECEPT IDT 8POS 1.27MM TIN
90327-0306 CONN RECEPT IDT 6POS 1.27MM TIN
90325-9004 CONN HEADER 4POS 1.27MM TIN T/H
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