參數(shù)資料
型號: AT32UC3A364-CTUT
廠商: Atmel
文件頁數(shù): 24/94頁
文件大小: 0K
描述: IC MCU 64KB FLASH 144TBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 840
系列: AVR®32 UC3 A3
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,WDT
輸入/輸出數(shù): 110
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-TFBGA
包裝: 托盤
配用: ATEVK1104-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
30
32072SH–AVR32–10/2012
AT32UC3A3
4.5
Exceptions and Interrupts
AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in Table 4-4 on page 33. Most of the han-
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
4.5.1
System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
92
368
MPUPSR4
MPU Privilege Select Register region 4
93
372
MPUPSR5
MPU Privilege Select Register region 5
94
376
MPUPSR6
MPU Privilege Select Register region 6
95
380
MPUPSR7
MPU Privilege Select Register region 7
96
384
MPUCRA
Unused in this version of AVR32UC
97
388
MPUCRB
Unused in this version of AVR32UC
98
392
MPUBRA
Unused in this version of AVR32UC
99
396
MPUBRB
Unused in this version of AVR32UC
100
400
MPUAPRA
MPU Access Permission Register A
101
404
MPUAPRB
MPU Access Permission Register B
102
408
MPUCR
MPU Control Register
103-191
448-764
Reserved
Reserved for future use
192-255
768-1020
IMPL
IMPLEMENTATION DEFINED
Table 4-3.
System Registers (Continued)
Reg #
Address
Name
Function
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