參數(shù)資料
型號(hào): AT32UC3A0512-CTUT
廠商: Atmel
文件頁(yè)數(shù): 75/97頁(yè)
文件大?。?/td> 0K
描述: IC MCU 512KB FLASH 144TFBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 840
系列: AVR®32 UC3 A0
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 109
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-TFBGA
包裝: 托盤(pán)
配用: ATEVK1105-ND - KIT EVAL FOR AT32UC3A0
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
77
AT32UC3A
When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if
CPOL=1 and CPHA=0.
4.
SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first
transfer
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
5.
SPI Disable does not work in Slave mode
Fix/workaround
Read the last received data then perform a Software reset.
15.3.4
Power Manager
1.
If the BOD level is higher than VDDCORE, the part is constantly under reset
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
15.3.5
Flashc
1.
On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,
EP, EA, WUP, EUP commands may happen
- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a
given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the
other half of the flash may fail. This may lead to an exception or to other errors derived from
this corrupted read access.
- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may
fail. This may lead to an exception or to other errors derived from this corrupted read access.
- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading
(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to
an exception or to other errors derived from this corrupted read access.
Fix/Workaround
Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or
through the EBI. After these commands, read twice one flash page initialized to 00h in each
half part of the flash.
15.3.6
PDCA
1.
Wrong PDCA behavior when using two PDCA channels with the same PID.
32058KS–AVR32–01/12
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