參數(shù)資料
型號(hào)： AT30TSE002B-MAH-T
廠商： Atmel
文件頁(yè)數(shù)： 17/36頁(yè)
文件大?。?/td> 1184K
描述： SENSOR DGTL TEMP I2C/SMBUS 8WDFN
標(biāo)準(zhǔn)包裝： 5,000
系列： *
 17
Atmel AT30TSE002B [DATASHEET]
8711GSEEPR5/12
Any JEDEC TSE2002av compliant temperature sensor can be configured to report an over temperature limit condition to
the host system via its
EVENT pin. These temperature sensors have the default value for all temperature alarm
thresholds set at 0癈.
Often, if a system designer determines to utilize only the Critical Alarm temperature threshold to trigger an Event, it is
likely he would only setup the Critical Alarm temperature threshold to a proper value while leaving the Upper Alarm
temperature threshold unchanged at the default (0癈).
Due to some ambiguity in the TSE2002av specification, it is possible a temperature sensor can process bit three (Event
Output Control) of the Configuration register first while others process bit two (Critical Temperature only) first from the
Configuration register. If both bits are set to Logic 1 state concurrently and bit three is processed first, the Event output
would be enabled before learning the Upper Alarm temperature threshold should be ignored. Since the Upper Alarm
temperature threshold is often left unchanged at 0癈 if it is not used and if the temperature sensor operates in a greater
than 0癈 environment, it naturally outputs an Event condition. Sometime later, after bit two is also processed, the
temperature sensor would ignore the Upper Alarm temperature threshold and deassert the Event output if the ambient
temperature has not exceeded the Critical Alarm temperature threshold; however, for a system that triggers action off
this Event output, this correction has arrived too late.
4
EVTSTS
EVENT Pin Output Status:
0 = The
EVENT Output is not asserted by the device (power-on default).
1 = The
EVENT Output is asserted due to an alarm trip condition.
Note:
This bit will be cleared when entering shutdown mode and will resume status update
immediately upon exiting shutdown.
3
EVTOUT
EVENT Output Control:
This bit, when set, prevents the
EVENT pin from generating an interrupt.
0 = The
EVENT output is disabled and will not generate interrupts (power-on default).
1 = The
EVENT output is enabled.
When either of the Crit_Alarm Trip or Alarm Window lock bits is set, this bit cannot be altered until
unlocked.
2
CRITEVT
Critical Temperature Only:
0 = The
EVENT output is asserted for the Upper, Lower, and Critical Alarms (power-on default).
1 = The
EVENT output is asserted for only Critical Alarm when ambient temperature > Crit_Alarm trip
boundary.
 When the Alarm Window lock bit is set, this bit cannot be altered until unlocked.
1
EVTPOL
EVENT Polarity:
0 = Active Low (power-on default). A pull-up resistor is required on this pin to set inactive state.
1 = Active High.
When either of the Crit_Alarm Trip or Alarm Window lock bits is set, this bit cannot be altered until
unlocked
0
EVTMOD
EVENT Mode:
0 = The
EVENT pin will operate in Comparator mode (power-on default).
1 = The
EVENT pin will operate in Interrupt mode.
When either of the Crit_Alarm Trip or Alarm Window lock bits is set, this bit cannot be altered until
unlocked.
Table 11-6.   Configuration Register Bit Description (Continued)
Bit
Symbol
Description
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