參數(shù)資料
型號(hào): AT29C020-15TI
廠商: ATMEL CORP
元件分類: DRAM
英文描述: High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125
中文描述: 256K X 8 FLASH 5V PROM, 150 ns, PDSO32
封裝: 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 257K
代理商: AT29C020-15TI
AC Read Characteristics
AT29C020-90
AT29C020-10
AT29C020-12
AT29C020-15
Symbol
t
ACC
t
CE
(1)
t
OE
(2)
t
DF
(3, 4)
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or
Address, whichever
occurred first
Min
Max
Min
Max
Min
Max
Min
Max
Units
ns
ns
ns
ns
0
90
90
40
25
100
100
50
25
120
120
50
30
150
150
70
40
0
0
0
0
0
0
0
0
t
OH
0
0
0
0
ns
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
Input Test Waveforms and Measurement Level
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
Output Test Load
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
C
IN
C
OUT
Note:
1. This parameter is characterized and is not 100% tested.
t
R
, t
F
< 5 ns
Note: While CE is active, any address inputs that cause V
IH
to drop
below 2.0V or V
IL
to rise above 0.8V for a duration of up to 15 ns
may cause the device to read incorrectly.
AT29C020
5
相關(guān)PDF資料
PDF描述
AT29C020-90JC High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125
AT29C020-90PC 2-Megabit 256K x 8 5-volt Only CMOS Flash Memory
AT29C020-90TC 2-Megabit 256K x 8 5-volt Only CMOS Flash Memory
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