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參數(shù)資料
| 型號： | AT29C020-10JC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-TSSOP -55 to 125 |
| 中文描述： | 256K X 8 FLASH 5V PROM, 100 ns, PQCC32 |
| 封裝： | PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 257K |
| 代理商： | AT29C020-10JC |
To allow for simple in-system reprogrammability, the
AT29C020 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the opera-
tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C020 is performed on a sector basis; 256-bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 256-
bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle
has been detected, a new access for a read or program
can begin.
Description
(Continued)
Device Operation
READ:
The AT29C020 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
BYTE LOAD:
Byte loads are used to enter the 256-
bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the WE or CE input with CE or WE low (re-
spectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE.
PROGRAM:
The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After
the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150
μ
s of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
μ
s of the last low to high transi-
tion, the load period will end and the internal programming
(continued)
Block Diagram
period will start. A8 to A17 specify the sector address. The
sector address must be valid during each high to low tran-
sition of WE (or CE). A0 to A7 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
WC
, a
read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION:
A software control-
led data protection feature is available on the AT29C020.
Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may
be performed. The software protection feature may be en-
abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en-
abled the same three program commands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector pro-
gram timing specifications. Once set, the software data
protection feature remains active unless its disable com-
mand is issued. Power transitions will not reset the soft-
ware data protection feature, however the software fea-
ture will guard against inadvertent program cycles during
power transitions.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
2
AT29C020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT29C020-10JI | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-TSSOP -55 to 125 |
| AT29C020-10PC | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-TSSOP -55 to 125 |
| AT29C020-10PI | 2-Megabit 256K x 8 5-volt Only CMOS Flash Memory |
| AT29C020-10TC | High Speed CMOS Logic Octal Inverting Transparent Latches with 3-State Outputs 20-PDIP -55 to 125 |
| AT29C020-10TI | High Speed CMOS Logic Octal Inverting Transparent Latches with 3-State Outputs 20-PDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT29C020-10JI | 功能描述:IC FLASH 2MBIT 100NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| AT29C020-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:2-Megabit 256K x 8 5-volt Only CMOS Flash Memory |
| AT29C020-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:2-Megabit 256K x 8 5-volt Only CMOS Flash Memory |
| AT29C020-10TC | 功能描述:IC FLASH 2MBIT 100NS 32TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| AT29C020-10TI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:2-Megabit 256K x 8 5-volt Only CMOS Flash Memory |
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