- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381445 > AT29BV040A-35 (Atmel Corp.) 4 Megabit 512K x 8 Single 2.7-volt Battery-Voltage CMOS Flash Memory PDF資料下載
參數(shù)資料
| 型號： | AT29BV040A-35 |
| 廠商： | Atmel Corp. |
| 英文描述： | 4 Megabit 512K x 8 Single 2.7-volt Battery-Voltage CMOS Flash Memory |
| 中文描述： | 4兆位為512k × 8單2.7伏電池電壓的CMOS閃存 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 431K |
| 代理商： | AT29BV040A-35 |
Device Operation
READ:
The AT29BV040A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
SOFTWARE DATA PROTECTION PROGRAMMING:
The AT29BV040 has 2048 individual sectors, each 256-
bytes. Using the software data protection feature, byte
loads are used to enter the 256-bytes of a sector to be
programmed. The AT29BV040A can only be programmed
or reprogrammed using the software data protection fea-
ture. The device is programmed on a sector basis. If a byte
of data within the sector is to be changed, data for the en-
tire 256-byte sector must be loaded into the device. The
AT29BV040A automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.
Software data protection protects the device from inadver-
tent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program op-
eration. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the software feature will guard against inadvertent pro-
gram cycles during power transitions.
Any attempt to write to the device without the 3-byte com-
mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
t
WC
, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
(continued)
Block Diagram
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 256-bytes of data must be loaded into each sector.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After
the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150
μ
s of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
μ
s of the last low to high transi-
tion, the load period will end and the internal programming
period will start. A8 to A18 specify the sector address. The
sector address must be valid during each high to low tran-
sition of WE (or CE). A0 to A7 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT29BV040A
in the following ways: (a) V
CC
sense— if V
CC
is below 1.8V
(typical), the program function is inhibited. (b) V
CC
power
on delay— once V
CC
has reached the V
CC
sense level,
the device will automatically time out 10 ms (typical) be-
fore programming. (c) Program inhibit— holding any one
of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter— pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
INPUT LEVELS:
While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs
(
OE,
CE and WE) may be driven from 0 to 5.5V without ad-
versely affecting the operation of the device. The I/O lines
can only be driven from 0 to V
CC
+ 0.6V.
4-24
AT29BV040A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT29BV040A-35TC | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-SOIC -55 to 125 |
| AT29BV040A-35TI | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-SOIC -55 to 125 |
| AT29C010-xxx | 1 Megabit 128K x 8 5-volt Only CMOS Flash Memory |
| AT29C010A-12JC | 1 Megabit 128K x 8 5-volt Only CMOS Flash Memory |
| AT29C010A-12JI | 1 Megabit 128K x 8 5-volt Only CMOS Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT29BV040A-35TC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:4 Megabit 512K x 8 Single 2.7-volt Battery-Voltage CMOS Flash Memory |
| AT29BV040A-35TI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:4 Megabit 512K x 8 Single 2.7-volt Battery-Voltage CMOS Flash Memory |
| AT29C010 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 Megabit 128K x 8 5-volt Only CMOS Flash Memory |
| AT29C010-12DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| AT29C010-12DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。