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參數(shù)資料
| 型號(hào)： | AT28C64B |
| 廠商： | Atmel Corp. |
| 元件分類： | DRAM |
| 英文描述： | 8K x 8 Parallel EEPROM with Page Write and Software Data Protection(8K x 8并行EEPROM帶分頁(yè)寫(xiě)數(shù)據(jù)保護(hù)和軟件數(shù)據(jù)保護(hù)) |
| 中文描述： | 8K的× 8的并行EEPROM，帶有頁(yè)寫(xiě)入和軟件數(shù)據(jù)保護(hù)（8K的× 8并行的EEPROM帶分頁(yè)寫(xiě)數(shù)據(jù)保護(hù)和軟件數(shù)據(jù)保護(hù)） |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大小： | 317K |
| 代理商： | AT28C64B |
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AT28C64B
7
Page Mode Write Waveforms
(1)(2)
Notes:
1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
t
S
= t
H
= 1 μsec (min.)
t
W
= 10 msec (min.)
V
H
= 12.0
±
0.5V
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
t
WC
Write Cycle Time
10
ms
t
WC
Write Cycle Time (option available; contact Atmel sales office for
ordering part number)
0
2
ms
t
AS
Address Setup Time
0
ns
t
AH
Address Hold Time
50
ns
t
DS
Data Setup Time
50
ns
t
DH
Data Hold Time
0
ns
t
WP
Write Pulse Width
100
ns
t
BLC
Byte Load Cycle Time
150
μs
t
WPH
Write Pulse Width High
50
ns
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| AT28C64B-15 | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-BGA MICROSTAR JUNIOR -40 to 85 |
| AT28C64B-15JC | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85 |
| AT28C64B-15JI | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT28C64B_06 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection |
| AT28C64B_09 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection |
| AT28C64B-15 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:64K (8K x 8) CMOS E2PROM with Page Write and Software Data Protection |
| AT28C64B-15DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| AT28C64B-15DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
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