參數(shù)資料
型號: AT28C64B-15SI
廠商: ATMEL CORP
元件分類: DRAM
英文描述: Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
中文描述: 8K X 8 EEPROM 5V, 150 ns, PDSO28
封裝: 0.300 INCH, PLASTIC, MS-013, SOIC-28
文件頁數(shù): 5/13頁
文件大?。?/td> 317K
代理商: AT28C64B-15SI
AT28C64B
5
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
Note:
1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol
Parameter
AT28C64B-15
AT28C64B-20
AT28C64B-25
Units
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
150
200
250
ns
t
CE
(1)
CE to Output Delay
150
200
250
ns
t
OE
(2)
OE to Output Delay
0
70
0
80
0
100
ns
t
DF
(3)(4)
CE or OE to Output Float
0
50
0
55
0
60
ns
t
OH
Output Hold from OE, CE or
Address, whichever occurred first
0
0
0
ns
t
R
, t
F
< 5 ns
Pin Capacitance
f = 1 MHz, T = 25
°
C
(1)
Symbol
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
相關(guān)PDF資料
PDF描述
AT28C64B-15TC Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-VQFN -40 to 85
AT28C64B-15TI Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-BGA MICROSTAR JUNIOR -40 to 85
AT28C64B-20 8-Bit Shift Registers With Output Registers 16-SSOP -40 to 85
AT28C64B-20JC 8-Bit Shift Registers With Output Registers 16-SSOP -40 to 85
AT28C64B-20JI 8-Bit Shift Registers With Output Registers 16-SOIC -40 to 85
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