參數(shù)資料
型號: AT27LV256A-90TC
廠商: ATMEL CORP
元件分類: DRAM
英文描述: High Speed CMOS Logic 14-Stage Binary Counter with Oscillator 16-TSSOP -55 to 125
中文描述: 32K X 8 OTPROM, 90 ns, PDSO28
封裝: PLASTIC, TSOP-28
文件頁數(shù): 8/9頁
文件大小: 221K
代理商: AT27LV256A-90TC
AC Programming Characteristics
T
A
= 25
±
5°C, V
CC
= 6.5
±
0.25V, V
PP
= 13.0
±
0.25V
Sym-
bol
Parameter
Test
Conditions*
(1)
Limits
Min
Units
Max
t
AS
t
OES
t
DS
t
AH
t
DH
Address Setup Time
2
μ
s
OE Setup Time
2
μ
s
Data Setup Time
2
μ
s
Address Hold Time
0
μ
s
Data Hold Time
OE High to
Output Float Delay
(2)
V
PP
Setup Time
2
μ
s
t
DFP
0
130
ns
t
VPS
t
VCS
t
PW
t
OE
2
μ
s
V
CC
Setup Time
CE Program Pulse Width
(3)
Data Valid from OE
(2)
V
PP
Pulse Rise Time
During Programming
2
μ
s
95
105
μ
s
150
ns
t
PRT
50
ns
*AC Conditions of Test:
Input Rise and Fall Times (10% to 90%)...........20 ns
Input Pulse Levels................................0.45V to 2.4V
Input Timing Reference Level...............0.8V to 2.0V
Output Timing Reference Level............0.8V to 2.0V
Notes: 1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
2. This parameter is only sampled and is not 100%
tested. Output Float is defined as the point where
data is no longer driven —see timing diagram.
3. Program Pulse width tolerance is 100
μ
sec
±
5%.
Atmel’s 27LV256A Integrated
Product Identification Code
(1)
Codes
Pins
Hex
Data
A0
O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer
Device Type
Note:
0
1
0
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1E
8C
1. The AT27LV256A has the same Product Identification
Code as the AT27C256R. Both are programming
compatible.
Rapid
Programming Algorithm
A 100
μ
s CE pulse width is used to program. The address
is set to the first location. V
CC
is raised to 6.5V and V
PP
is
raised to 13.0V. Each address is first programmed with
one 100
μ
s CE pulse without verification. Then a verifica-
tion / reprogramming loop is executed for each address.
In the event a byte fails to pass verification, up to 10 suc-
cessive 100
μ
s pulses are applied with a verification after
each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte
verifies properly, the next address is selected until all have
been checked. V
PP
is then lowered to 5.0V and V
CC
to
5.0V. All bytes are read again and compared with the
original data to determine if the device passes or fails.
3-82
AT27LV256A
相關(guān)PDF資料
PDF描述
AT27LV256A-90TI High Speed CMOS Logic 14-Stage Binary Counter with Oscillator 16-TSSOP -55 to 125
AT27LV256A-12 High Speed CMOS Logic CMOS Programmable Divide-by-N Counter 24-PDIP -55 to 125
AT27LV256A-12JC High Speed CMOS Logic CMOS Programmable Divide-by-N Counter 24-PDIP -55 to 125
AT27LV256A-12JI High Speed CMOS Logic CMOS Programmable Divide-by-N Counter 24-SOIC -55 to 125
AT27LV256A-12RC High Speed CMOS Logic CMOS Programmable Divide-by-N Counter 24-SOIC -55 to 125
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參數(shù)描述
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