- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381433 > AT27LV1026-45 (Atmel Corp.) High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-SO -55 to 125 PDF資料下載
參數(shù)資料
| 型號： | AT27LV1026-45 |
| 廠商： | Atmel Corp. |
| 英文描述： | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-SO -55 to 125 |
| 中文描述： | 1兆2 × 32K的× 16 16位交錯低電壓檢察官辦公室存儲器 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 175K |
| 代理商： | AT27LV1026-45 |
AT27LV1026
2
This device is internally architected as two 32K x 16 mem-
ory banks, odd and even. To begin a non-linear access
NLA cycle, (which typically equals a minimum of two linear
access LA cycles), ALE is asserted high and CS is
asserted low. The two internal 15-bit counters store the
address for the odd and even banks and increment alter-
nately during each subsequent linear access LA cycle. The
LA cycle will be terminated when CS is asserted high put-
ting the device in standby mode, or another NLA cycle
starts. The LA cycle can be resumed when CS is asserted
low and ALE stays low. The AT27LV1026 will continuously
output data within each LA cycle which is determined by
the read RD signal. Continuous interleave read operation is
possible as there is no physical limit to the linear access LA
output. When the last address in the array is reached the
counters will wrap around to the first address location and
continue.
For a NLA cycle where A0 = 0 (ALE asserted high, CS
asserted low), both even and odd counters will be loaded
with new address (A1 - A15). Outputs (O0 - O15) from the
even bank will be valid in t
ACCNLA
within the NLA cycle, the
outputs from the odd bank will become valid in t
ACCLA
within
the following LA cycle while the even counter increments
by one to ready the data out for the next LA cycle. The out-
puts will have even or odd data alternating and the
counters increment for the consecutive LA cycles until CS
is asserted high putting the device in standby mode, or a
new NLA cycle begins.
For a NLA cycle where A0 = 1 (ALE asserted high, CS
asserted low), the odd counter will be loaded with the new
address (A1 - A15) while the even counter gets loaded with
the new address+1. Outputs (O0 - O15) from odd bank of
memory will be valid in t
ACCNLA
within the NLA cycle, the
data output from the even bank of memory will become
valid in t
ACCLA
within the following LA cycle while the odd
counter increments by one to ready the data out for the
next LA cycle. The outputs will have data from the odd or
even memory bank alternately and the counters increment
for the following consecutive LA cycles until CS is asserted
high putting the device in standby mode, or a new NLA
cycle begins. When coming out of standby mode, the
device can either enter into a new NLA cycle or resume
where the previous LA operation left off and was termi-
nated by standby mode.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a 0.1
μ
F high frequency, low inherent inductance, ceramic
capacitor should be utilized for each device. This capacitor
should be connected between the V
CC
and Ground termi-
nals of the device, as close to the device as possible. Addi-
tionally, to stabilize the supply voltage level on printed cir-
cuit boards with large EPROM arrays, a 4.7
μ
F bulk elec-
trolytic capacitor should be utilized, again connected
between the V
CC
and Ground terminals. This capacitor
should be positioned as close as possible to the point
where the power supply is connected to the array.
Operating Table
If A0 = 0 at beginning of NLA cycle:
If A0 = 1 at beginning of NLA cycle:
and so on.
and so on.
Consecutive
Cycle
Counter
Outputs
Consecutive
Cycle
Counter
Outputs
Even
Odd
Even
Odd
NLA
Address
Address
from Even Bank
NLA
Address+1
Address
from Odd Bank
LA
+1
-
from Odd Bank
LA
-
+1
from Even Bank
LA
-
+1
from Even Bank
LA
+1
-
from Odd Bank
LA
+1
-
from Odd Bank
LA
-
+1
from Even Bank
LA
-
+1
from Even Bank
LA
+1
-
from Odd Bank
Standby
HiZ
Standby
HiZ
LA
+1
-
from Odd Band
LA
-
+1
from Even Bank
LA
-
+1
from Even Bank
LA
+1
-
from Odd Band
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT27LV1026-45JC | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-SO -55 to 125 |
| AT27LV1026-45JI | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-TSSOP -55 to 125 |
| AT27LV1026-45VC | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-TSSOP -55 to 125 |
| AT27LV1026-45VI | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-TSSOP -55 to 125 |
| AT27LV1026-55 | High Speed CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers 16-TSSOP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT27LV256A-12JC | 功能描述:可擦除可編程ROM 256k bit RoHS:否 制造商:Maxim Integrated 類型: 存儲容量:1024 bit 組織:1 K x 1 接口類型: 工作電流:5 uA 編程電壓: 工作電源電壓:2.8 V to 6 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:TO-92 |
| AT27LV256A-12JI | 功能描述:IC OTP 256KBIT 120NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:32 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:1M (128K x 8) 速度:120ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:32-LCC（J 形引線） 供應商設(shè)備封裝:32-PLCC 包裝:管件 其它名稱:AT49BV00112JC |
| AT27LV256A-12RC | 功能描述:IC OTP 256KBIT 120NS 28SOIC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:32 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:1M (128K x 8) 速度:120ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:32-LCC（J 形引線） 供應商設(shè)備封裝:32-PLCC 包裝:管件 其它名稱:AT49BV00112JC |
| AT27LV256A-12RI | 功能描述:IC OTP 256KBIT 120NS 28SOIC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:32 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:1M (128K x 8) 速度:120ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:32-LCC（J 形引線） 供應商設(shè)備封裝:32-PLCC 包裝:管件 其它名稱:AT49BV00112JC |
| AT27LV256A-12TC | 功能描述:IC OTP 256KBIT 120NS 28TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:32 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:1M (128K x 8) 速度:120ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:32-LCC（J 形引線） 供應商設(shè)備封裝:32-PLCC 包裝:管件 其它名稱:AT49BV00112JC |
發(fā)布緊急采購，3分鐘左右您將得到回復。