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參數(shù)資料
| 型號(hào)： | AT27C256R-70 |
| 廠商： | Atmel Corp. |
| 英文描述： | 256K 32K x 8 OTP CMOS EPROM |
| 中文描述： | 256K 32K的× 8檢察官辦公室的CMOS存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | AT27C256R-70 |
AC Programming Characteristics
T
A
= 25
±
5°C, V
CC
= 6.5
±
0.25V, V
PP
= 13.0
±
0.25V
Sym-
bol
Parameter
Test
Conditions*
(1)
Limits
Min
Units
Max
t
AS
t
OES
Address Setup Time
2
μ
s
OE Setup Time
Data Setup
Time
Address Hold Time
2
μ
s
t
DS
2
μ
s
t
AH
t
DH
0
μ
s
Data Hold Time
OE High to Out-
put Float Delay
(2)
V
PP
Setup
Time
V
CC
Setup
Time
CE Program
Pulse Width
(3)
Data
Valid from OE
(2)
V
PP
Pulse Rise Time During
Programming
2
μ
s
t
DFP
0
130
ns
t
VPS
2
μ
s
t
VCS
2
μ
s
t
PW
95
105
μ
s
t
OE
150
ns
t
PRT
50
ns
*AC Conditions of Test:
Input Rise and Fall Times (10% to 90%)..............20 ns
Input Pulse Levels...................................0.45V to 2.4V
Input Timing Reference Level...................0.8V to 2.0V
Output Timing Reference Level................0.8V to 2.0V
Notes: 1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
2. This parameter is only sampled and is not 100%
tested. Output Float is defined as the point where
data is no longer driven — see timing diagram.
3. Program Pulse width tolerance is 100
μ
sec
±
5%.
Atmel’s 27C256R Integrated
Product Identification Code
Codes
Pins
Hex
Data
A0
O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer
Device Type
0
1
0
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1E
8C
Rapid
Programming Algorithm
A 100
μ
s CE pulse width is used to program. The address
is set to the first location. V
CC
is raised to 6.5V and V
PP
is
raised to 13.0V. Each address is first programmed with
one 100
μ
s CE pulse without verification. Then a verifica-
tion/reprogramming loop is executed for each address. In
the event a byte fails to pass verification, up to 10 succes-
sive 100
μ
s pulses are applied with a verification after
each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte
verifies properly, the next address is selected until all have
been checked. V
PP
is then lowered to 5.0V and V
CC
to
5.0V. All bytes are read again and compared with the origi-
nal data to determine if the device passes or fails.
AT27C256R
3-131
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT27C256R-70JC | 256K 32K x 8 OTP CMOS EPROM |
| AT27C256R-70JI | High-Speed CMOS Logic Phase-Locked Loop with VCO 16-SO -40 to 85 |
| AT27C256R-70PC | 256K 32K x 8 OTP CMOS EPROM |
| AT27C256R-70PI | High-Speed CMOS Logic Phase-Locked Loop with VCO 16-SO -40 to 85 |
| AT27C256R-70RC | 256K 32K x 8 OTP CMOS EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT27C256R-70DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| AT27C256R-70DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| AT27C256R-70DM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| AT27C256R-70DM/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| AT27C256R-70JA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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