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參數(shù)資料
| 型號： | AT25HP256-10PC-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-SOIC -55 to 125 |
| 中文描述： | 32K X 8 SPI BUS SERIAL EEPROM, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 178K |
| 代理商： | AT25HP256-10PC-2.7 |
AT25HP256/512
6
Serial Interface Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an
input, the AT25HP256/512 always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25HP256/512 has
separate pins designated for data transmission (SO) and
reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no
data will be shifted into the AT25HP256/512, and the serial
output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize
the serial communication.
CHIP SELECT:
The AT25HP256/512 is selected when the
CS pin is low. When the device is not selected, data will not
be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS
pin to select the AT25HP256/512. When the device is
selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master
device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status regis-
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the
status register. The WP pin function is blocked when the
WPEN bit in the status register is “0”. This will allow the
user to install the AT25HP256/512 in a system with the WP
pin tied to ground and still be able to write to the status reg-
ister. All WP pin functions are enabled when the WPEN bit
is set to “1”.
SPI Serial Interface
AT25HP256/512
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25HP256-10PI | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-SOIC -55 to 125 |
| AT25HP256-10PI-2.7 | High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-PDIP -55 to 125 |
| AT25HP256W-10SI-2.7 | SPI Serial EEPROMs |
| AT25HP512 | High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125 |
| AT25HP512-10PC | High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25HP256-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25HP256-10PI-1.8 | 功能描述:IC EEPROM 256KBIT 10MHZ 8DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| AT25HP256-10PI-2.7 | 功能描述:IC EEPROM 256KBIT 10MHZ 8DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| AT25HP256C1-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25HP256C1-10CC-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
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