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參數(shù)資料
| 型號： | AT25F2048N-10SU-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 24 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 256K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大小： | 257K |
| 代理商： | AT25F2048N-10SU-2.7 |
9
AT25F2048
2455D–SEEPR–7/04
The WRSR instruction also allows the user to enable or disable the Write Protect (WP)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the locked-out sectors in the memory array are disabled. Write is
only allowed to sectors of the memory which are not locked out. The WRSR instruction
is self-timed to automatically erase and program BP0, BP1, and WPEN bits. In order to
write the status register, the device must first be write enabled via the WREN instruction.
Then, the instruction and data for the three bits are entered. During the internal write
cycle, all instructions will be ignored except RDSR instructions. The AT25F2048 will
automatically return to write disable state at the completion of the WRSR cycle.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
READ (READ):
Reading the AT25F2048 via the SO (Serial Output) pin requires the fol-
lowing sequence. After the CS line is pulled low to select a device, the READ instruction
is transmitted via the SI line followed by the byte address to be read (Refer to Table 6).
Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the speci-
fied address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The READ instruction can be contin-
ued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous READ
instruction.
PROGRAM (PROGRAM):
In order to program the AT25F2048, two separate instruc-
tions must be executed. First, the device must be write enabled via the WREN
instruction. Then the PROGRAM instruction can be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field loca-
tion selected by the Block Write Protection Level. During an internal self-timed
programming cycle, all commands will be ignored except the RDSR instruction.
The PROGRAM instruction requires the following sequence. After the CS line is pulled
low to select the device, the PROGRAM instruction is transmitted via the SI line followed
by the byte address and the data (D7-D0) to be programmed (Refer to Table 6). Pro-
gramming will start after the CS pin is brought high. The low-to-high transition of the CS
pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data
bit for mode 0.
The READY/BUSY status of the device can be determined by initiating a RDSR instruc-
tion. If Bit 0 = 1, the program cycle is still in progress. If Bit 0 = 0, the program cycle has
ended. Only the RDSR instruction is enabled during the program cycle.
Table 5.
WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
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