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參數(shù)資料
| 型號(hào)： | AT25F1024AN-10SU-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | SPI Serial Memory |
| 中文描述： | 128K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 299K |
| 代理商： | AT25F1024AN-10SU-2.7 |
5
3346C–SEEPR–7/04
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the AT25F1024A
always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25F1024A has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25F1024A, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT:
The AT25F1024A is selected when the CS pin is low. When the device
is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the AT25F1024A.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The AT25F1024A has a write lockout feature that can be activated
by asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is “1”, all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25F1024A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25F1024AY4-10YU-2.7 | SPI Serial Memory |
| AT25F1024A | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-PDIP -55 to 125 |
| AT25F1024 | High Speed CMOS Logic Hex Buffers/Line Drivers with Non-Inverting 3-State Outputs 16-SOIC -55 to 125 |
| AT25F512 | SPI Serial Memory |
| AT25F512N-10SI-2.7 | SPI Serial Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25F1024AY4-10YU-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1Mbit High Speed SPI Serial Flash Memory 1M (131,072 x 8) |
| AT25F1024C1-10CC-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| AT25F1024C1-10CI-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| AT25F1024N-10SI-2.7 | 制造商:Atmel Corporation 功能描述:Flash Serial-SPI 3V/3.3V 1Mbit 128K x 8bit 20ns 8-Pin SOIC |
| AT25F1024N-10SU-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial Memory |
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