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參數(shù)資料
| 型號(hào)： | AT25256-10CC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs 20-PDIP -55 to 125 |
| 中文描述： | 32K X 8 SPI BUS SERIAL EEPROM, CDSO8 |
| 封裝： | 0.230 INCH, LAP-8 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 230K |
| 代理商： | AT25256-10CC |
AT25128/256
6
Serial Interface Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an
input, the AT25128/256 always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25128/256 has
separate pins designated for data transmission (SO) and
reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no
data will be shifted into the AT25128/256, and the serial
output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize
the serial communication.
CHIP SELECT:
The AT25128/256 is selected when the CS
pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS
pin to select the AT25128/256. When the device is selected
and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device
without resetting the serial sequence. To pause, the HOLD
pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status regis-
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the
status register. The WP pin function is blocked when the
WPEN bit in the status register is “0”. This will allow the
user to install the AT25128/256 in a system with the WP pin
tied to ground and still be able to write to the status regis-
ter. All WP pin functions are enabled when the WPEN bit is
set to “1”.
SPI Serial Interface
AT25128/256
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25256-10CI | High Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs 20-PDIP -55 to 125 |
| AT25256-10PC | High Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs 20-SOIC -55 to 125 |
| AT25256-10PC-1.8 | High Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs 20-SOIC -55 to 125 |
| AT25256-10PC-2.7 | High Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs 20-SOIC -55 to 125 |
| AT25256-10PI | SPI Serial EEPROMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25256-10CC-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25256-10CC-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25256-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25256-10CI-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25256-10CI-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
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