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參數(shù)資料
| 型號： | AT25128AN-10SE-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | SPI Serial Extended Temperature EEPROMs |
| 中文描述： | 16K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 390K |
| 代理商： | AT25128AN-10SE-2.7 |
8
AT25128A/256A
5088C–SEEPR–11/04
Top quarter, top half, or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be read only. The block write protection levels
and corresponding status register control bits are shown in Table 8.
Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g., WREN, t
WC
, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory that are not block-protected.
NOTE:
When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
READ SEQUENCE (READ):
Reading the AT25128A/256A via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the spec-
ified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address, allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE):
In order to program the AT25128A/256A, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field loca-
Table 8.
Block Write Protect Bits
Level
Status Register Bits
Array Addresses Protected
BP1
BP0
AT25128A
AT25256A
0
0
0
None
None
1 (1/4)
0
1
3000–3FFF
6000–7FFF
2 (1/2)
1
0
2000–3FFF
4000–7FFF
3 (All)
1
1
0000–3FFF
0000–7FFF
Table 9.
WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
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| AT25128AN-10SI-2.7-T | 功能描述:IC EEPROM 128KBIT 20MHZ 8SOIC 制造商:microchip technology 系列:- 包裝:帶卷（TR） 零件狀態(tài):停產(chǎn) 存儲器類型:非易失 存儲器格式:EEPROM 技術(shù):EEPROM 存儲容量:128Kb （16K x 8） 時鐘頻率:20MHz 寫周期時間 - 字，頁:5ms 存儲器接口:SPI 電壓 - 電源:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SOIC 基本零件編號:AT25128 標(biāo)準(zhǔn)包裝:3,000 |
| AT25128AN10SI27 | 制造商:Atmel Corporation 功能描述: |
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