參數(shù)資料
型號(hào): AT25080AN-10SU-2.7
廠商: ATMEL CORP
元件分類: DRAM
英文描述: Connector Kit; Contents Of Kit:C14610G0166061 16 position hood PG 21 single latch top entry, C14610A0161021 16 position male insert wire protect, VN162100014 PG 21 gland bushing, For 0.433" - 0.866" diameter cable RoHS Compliant: Yes
中文描述: 1K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8
文件頁數(shù): 1/20頁
文件大?。?/td> 388K
代理商: AT25080AN-10SU-2.7
1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
Medium-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
Extended Temperature Range –40
°
C to 125
°
C
5.0 MHz Clock Rate
32-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (2 ms [5V] typical)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
8-lead PDIP, 8-lead JEDEC SOIC Packages and 8-lead TSSOP Packages
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial
electrically-erasable programmable read-only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT25080A/160A/320A/640A is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC and 8-lead TSSOP packages.
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely self-
timed, and no separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate program enable and program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Table 1.
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
DC
Don’t Connect
SPI Serial
Extended
Temperature
EEPROMs
8K (1024 x 8)
16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)
AT25080A
AT25160A
AT25320A
AT25640A
5082B–SEEPR–1/05
1
2
3
4
8
7
6
5
C
S
S
O
WP
GND
VCC
HOLD
S
CK
S
I
8
-le
a
d PDIP
1
2
3
4
8
7
6
5
C
S
S
O
WP
GND
VCC
HOLD
S
CK
S
I
8
-le
a
d T
SS
OP
1
2
3
4
8
7
6
5
C
S
S
O
WP
GND
VCC
HOLD
S
CK
S
I
8
-le
a
d
S
OIC
相關(guān)PDF資料
PDF描述
AT25080A-10PE-2.7 CAP 4.7UF 10V 20% TANT SMD-2012-15 TR-7-PL
AT25160A-10PE-2.7 SPI Serial EEPROMs
AT25320A-10PE-2.7 SPI Serial EEPROMs
AT25640A-10PE-2.7 SPI Serial EEPROMs
AT25320A-10TQ-2.7 128 x 64 pixel format, LED Backlight available
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