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參數(shù)資料
| 型號(hào)： | AT25040 |
| 廠商： | Atmel Corp. |
| 英文描述： | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| 中文描述： | 高速CMOS邏輯3/8線性反相/同相解碼多路解復(fù)用器 TSSOP-16封裝 工作溫度：-55℃_125℃ |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | AT25040 |
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AT25010/020/040
7
Functional Description
The AT25010/020/040 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Note:
WRITE ENABLE (WREN):
the write disable state when V
CC
is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction. The WP pin must be held high during a
WREN instruction.
WRITE DISABLE (WRDI):
To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR):
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
“A” represents MSB address bit A8.
The device will power up in
The Read Status
WRITE STATUS REGISTER (WRSR):
instruction allows the user to select one of four levels of
protection. The AT25010/020/040 is divided into four array
segments. Top quarter (1/4), Top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have
the same properties and functions as the regular memory
cells (e.g. WREN, t
WC
, RDSR).
The WRSR
READ
AT25010/020/040 via the SO (Serial Output) pin requires
the following sequence. After the CS line is pulled low to
select a device, the READ op-code (including A8) is trans-
mitted via the SI line followed by the byte address to be
read (A7-A0). Upon completion, any data on the SI line will
be ignored. The data (D7-D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be
read, the CS line should be driven high after the data
comes out. The READ sequence can be continued since
the byte address is automatically incremented and data will
continue to be shifted out. When the highest address is
reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one con-
tinuous READ cycle.
SEQUENCE
(READ):
Reading
the
Table 1.
Instruction Set for the AT25010/020/040
Instruction
Name
Instruction
Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 A011
Read Data from Memory Array
WRITE
0000 A010
Write Data to Memory Array
Table 2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is notWRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
Table 4.
Block Write Protect Bits
Level
Status
Register Bits
Array Addresses Protected
BP1
BP0
AT25010
AT25020
AT25040
0
0
0
None
None
None
1 (1/4)
0
1
60-7F
C0-FF
180-1FF
2 (1/2)
1
0
40-7F
80-FF
100-1FF
3 (All)
1
1
00-7F
00-FF
000-1FF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25040-10PC | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25040-10PC-1.8 | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25040-10PC-2.7 | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25040-10PI | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25040-10PA-2.7C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|512X8|CMOS|DIP|8PIN|PLASTIC |
| AT25040-10PA-5.0C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|512X8|CMOS|DIP|8PIN|PLASTIC |
| AT25040-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25040-10PC-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25040-10PC-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
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