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參數(shù)資料
| 型號(hào)： | AT25020N-10SC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | SPI Serial EEPROMs |
| 中文描述： | 256 X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | AT25020N-10SC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
AT25010/020/040
7
Functional Description
The AT25010/020/040 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Note:
WRITE ENABLE (WREN):
the write disable state when V
CC
is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction. The WP pin must be held high during a
WREN instruction.
WRITE DISABLE (WRDI):
To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR):
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
“A” represents MSB address bit A8.
The device will power up in
The Read Status
WRITE STATUS REGISTER (WRSR):
instruction allows the user to select one of four levels of
protection. The AT25010/020/040 is divided into four array
segments. Top quarter (1/4), Top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have
the same properties and functions as the regular memory
cells (e.g. WREN, t
WC
, RDSR).
The WRSR
READ
AT25010/020/040 via the SO (Serial Output) pin requires
the following sequence. After the CS line is pulled low to
select a device, the READ op-code (including A8) is trans-
mitted via the SI line followed by the byte address to be
read (A7-A0). Upon completion, any data on the SI line will
be ignored. The data (D7-D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be
read, the CS line should be driven high after the data
comes out. The READ sequence can be continued since
the byte address is automatically incremented and data will
continue to be shifted out. When the highest address is
reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one con-
tinuous READ cycle.
SEQUENCE
(READ):
Reading
the
Table 1.
Instruction Set for the AT25010/020/040
Instruction
Name
Instruction
Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 A011
Read Data from Memory Array
WRITE
0000 A010
Write Data to Memory Array
Table 2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is notWRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
Table 4.
Block Write Protect Bits
Level
Status
Register Bits
Array Addresses Protected
BP1
BP0
AT25010
AT25020
AT25040
0
0
0
None
None
None
1 (1/4)
0
1
60-7F
C0-FF
180-1FF
2 (1/2)
1
0
40-7F
80-FF
100-1FF
3 (All)
1
1
00-7F
00-FF
000-1FF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25040N-10SC | SPI Serial EEPROMs |
| AT25010AN-10SE-2.7 | DIN Audio Connector; No. of Contacts:7; Contact Termination:Solder; Mounting Type:Panel; Gender:Female; Terminal Type:Solder RoHS Compliant: Yes |
| AT25020AN-10SE-2.7 | DIN Audio Connector; No. of Contacts:8; Contact Termination:Solder; Mounting Type:Panel; Gender:Female; Terminal Type:Solder RoHS Compliant: Yes |
| AT25040AN-10SE-2.7 | DIN Audio Connector; No. of Contacts:4; Contact Termination:Solder; Mounting Type:Panel; Gender:Male; Terminal Type:Solder RoHS Compliant: Yes |
| AT25010AN-10SQ-2.7 | Connector Kit; Contents Of Kit:C14610G0065068 6 position hood PG 21 single latch high profile side entry, C14610A0061021 6 position male insert wire protect, VN162100014 PG 21 gland bushing, For 0.433" - 0.866" diameter cable RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25020N-10SC-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25020N-10SC-2.7 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 SO-8 2K (256X8) 2.7V RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT25020N-10SE-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| AT25020N-10SI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 RO 511-M95020-WMN6 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT25020N-10SI-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
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