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參數(shù)資料
| 型號： | AT25020N-10SC-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| 中文描述： | 256 X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 165K |
| 代理商： | AT25020N-10SC-2.7 |
AT25010/020/040
8
WRITE SEQUENCE (WRITE):
AT25010/020/040, the Write Protect pin (WP) must be held
high and two separate instructions must be executed. First,
the device
must be write enabled
via the Write Enable
(WREN) Instruction. Then a Write (WRITE) Instruction may
be executed. Also, the address of the memory location(s)
to be programmed must be outside the protected address
field location selected by the Block Write Protection Level.
During an internal write cycle, all commands will be ignored
except the RDSR instruction.
A Write Instruction requires the following sequence. After
the CS line is pulled low to select the device, the WRITE
op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address (A7-A0) and the data (D7-D0) to
be programmed. Programming will start after the CS pin is
brought high. (The LOW to High transition of the CS pin
must occur during the SCK low time immediately after
clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined
by initiating a READ STATUS REGISTER (RDSR) Instruc-
In order to program the
tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro-
gramming cycle.
The AT25010/020/040 is capable of an 8-byte PAGE
WRITE operation. After each byte of data is received, the
three low order address bits are internally incremented by
one; the six high order bits of the address will remain con-
stant. If more than 8 bytes of data are transmitted, the
address counter will roll over and the previously written
data will be overwritten. The AT25010/020/040 is automati-
cally returned to the write disable state at the completion of
a WRITE cycle.
Note:
If the WP pin is brought low or if the device is not Write
enabled (WREN), the device will ignore the Write instruc-
tion and will return to the standby state, when CS is
brought high. A new CS falling edge is required to re-ini-
tiate the serial communication.
相關PDF資料 |
PDF描述 |
|---|---|
| AT25020N-10SI | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25020N-10SI-1.8 | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25020N-10SI-2.7 | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25040 | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
| AT25040-10PC | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting 16-TSSOP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT25020N-10SE-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| AT25020N-10SI | 功能描述:電可擦除可編程只讀存儲器 RO 511-M95020-WMN6 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT25020N-10SI-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25020N-10SI-2.7 | 功能描述:電可擦除可編程只讀存儲器 2K (256X8) 2.7V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT25020Y1-10YI-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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