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參數(shù)資料
| 型號： | AT24C21 |
| 廠商： | Atmel Corp. |
| 英文描述： | Triple 3-Input Positive-NOR Gate 14-TSSOP -40 to 85 |
| 中文描述： | 2線串行EEPROM |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 252K |
| 代理商： | AT24C21 |
AT24C21
5
Functional Description
The AT24C21 has two modes of operation: the Transmit-
Only Mode and the Bidirectional Mode. There is a separate
2-wire protocol to support each mode, each having a sepa-
rate clock input (SCL and VCLK) and both modes sharing a
common Bidirectional data line (SDA). The AT24C21
enters the Transmit-Only Mode upon powering up the
device. In this mode, the device transmits data on the SDA
pin upon a clock signal on the VCLK pin. The device will
remain in the Transmit-Only Mode until a valid high-to-low
transition takes place on the SCL pin. The device will
switch into the Bidirectional Mode when a valid transition
on the SCL pin is recognized. Once the device has transi-
tioned to the Bidirectional Mode, there is no way to return to
the Transmit-Only Mode, except to power down (reset) the
device.
Transmit-Only Mode (DDC1)
The AT24C21 will power up in the Transmit-Only Mode. In
this mode, the device will output one bit of data on the SDA
pin on each rising edge on the VCLK pin. Data is transmit-
ted in 8 bit words with the most significant bit first. Each
word is followed by a 9th “don't care” bit which will be in
high impedance state (refer to Figure 1). The AT24C21 will
continuously cycle through the entire memory array in
incremental sequence as long a VCLK is present and no
falling edges on SCL are received. When the maximum
address (7FH) is reached, the output will wrap around to
the zero location (00H) and continue. The Bidirectional
mode clock (SCL) pin must be held high for the device to
remain in the Transmit-Only mode.
Upon power-up, the AT24C21 will not output valid data until
it has been initialized. During initialization, data will not be
available until after the first nine clocks are sent to the
device (refer to Figure 2). The starting address for the
Transmit-Only mode can be determined during initializa-
tion. If the SDA pin is held high during the first eight clocks
(refer to Figure 2), the starting address will be 7FH. If the
SDA pin is low during the first eight clocks, the starting
address will be 00H. During the ninth clock, SDA should be
in high impedance.
Figure 1.
Transmit-Only Mode
Figure 2.
Device Initialization for Transmit-Only Mode
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