參數(shù)資料
型號(hào): AT24C04A
廠商: Atmel Corp.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁數(shù): 7/20頁
文件大小: 523K
代理商: AT24C04A
7
AT24C02A/04A/08A/16A
5083A–SEEPR–9/04
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition as SDA is high.
Figure 4.
Bus Timing
Figure 5.
Write Cycle Timing
Note:
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.
t
wr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
相關(guān)PDF資料
PDF描述
AT24C04A-10PE-2.7 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
AT24C04A-10PQ-2.7 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
AT24C04A-10TE-2.7 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
AT24C04A-10TQ-2.7 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
AT24C04AN-10SE-2.7 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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