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      參數(shù)資料
      型號(hào): AT24C04-10PC
      廠商: ATMEL CORP
      元件分類(lèi): DRAM
      英文描述: 2-Wire Serial EEPROM
      中文描述: 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
      封裝: 0.300 INCH, PLASTIC, DIP-8
      文件頁(yè)數(shù): 8/14頁(yè)
      文件大?。?/td> 261K
      代理商: AT24C04-10PC
      8
      AT24C01ASC/02SC/04SC/08SC/16SC
      1610B
      SEEPR
      04/04
      Write Operations
      BYTE WRITE:
      A write operation requires an 8-bit data word address following the
      device address word and acknowledgment. Upon receipt of this address, the EEPROM
      will again respond with a
      0
      (ACK) and then clock in the first 8-bit data word. Following
      receipt of the 8-bit data word, the EEPROM will output a
      0
      (ACK) and the addressing
      device, such as a microcontroller, must terminate the write sequence with a stop condi-
      tion. At this time the EEPROM enters an internally-timed write cycle, t
      WR
      , to the
      nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
      not respond until the write is complete (refer to Figure 7).
      Figure 7.
      Byte Write
      PAGE WRITE:
      The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,
      and 16K devices are capable of 16-byte page writes.
      A page write is initiated the same as a byte write, but the microcontroller does not send
      a stop condition after the first data word is clocked in. Instead, after the EEPROM
      acknowledges receipt of the first data word, the microcontroller can transmit up to 7
      (1K/2K) or 15 (4K, 8K, 16K) more data words. The EEPROM will respond with a
      0
      (ACK) after each data word received. The microcontroller must terminate the page write
      sequence with a stop condition (refer to Figure 8).
      Figure 8.
      Page Write
      Note:
      * = DON
      T CARE bit for 1K
      The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
      incremented following the receipt of each data word. The higher data word address bits
      are not incremented, retaining the memory page row location. When the word address,
      internally generated, reaches the page boundary, the following byte is placed at the
      beginning of the same page. If more than eight (1K/2K) or 16 (4K, 8K, 16K) data words
      are transmitted to the EEPROM, the data word address will
      roll over
      and previous data
      will be overwritten.
      ACKNOWLEGE POLLING:
      Once the internally timed write cycle has started and the
      EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
      ing a start condition followed by the device address word. The read/write bit is
      representative of the operation desired. Only if the internal write cycle has completed
      W
      R
      I
      T
      E
      S
      T
      A
      R
      T
      WORD ADDRESS
      L
      S
      B
      DATA
      S
      T
      O
      P
      *
      (n)
      DATA (n)
      DATA (n + 1)
      DATA (n + x)
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      參數(shù)描述
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