參數(shù)資料
型號: AT24C02BU3-10UU-1.8
廠商: ATMEL CORP
元件分類: DRAM
英文描述: Two-wire Serial EEPROM
中文描述: 256 X 8 I2C/2-WIRE SERIAL EEPROM, PBGA8
封裝: 1.50 X 2 MM, 0.50 MM PITCH, GREEN, DBGA2-8
文件頁數(shù): 6/20頁
文件大小: 413K
代理商: AT24C02BU3-10UU-1.8
6
AT24C02B
5126B–
S
EEPR–10/05
Device Operation
CLOCK and DATA TRANSITIONS:
The
S
DA pin is norm
a
lly pulled high with
a
n exter-
n
a
l device. D
a
t
a
on the
S
DA pin m
a
y ch
a
nge only during
S
CL low time periods (see
Figure 4 on p
a
ge 7). D
a
t
a
ch
a
nges during
S
CL high periods will indic
a
te
a
st
a
rt or stop
condition
a
s defined
b
elow.
START CONDITION:
A high-to-low tr
a
nsition of
S
DA with
S
CL high is
a
st
a
rt condition
which must precede
a
ny other comm
a
nd (see Figure 5 on p
a
ge
8
).
STOP CONDITION:
A low-to-high tr
a
nsition of
S
DA with
S
CL high is
a
stop condition.
After
a
re
a
d sequence, the stop comm
a
nd will pl
a
ce the EEPROM in
a
st
a
nd
b
y power
mode (see Figure 5 on p
a
ge
8
).
ACKNOWLEDGE:
All
a
ddresses
a
nd d
a
t
a
words
a
re seri
a
lly tr
a
nsmitted to
a
nd from the
EEPROM in
8
-
b
it words. The EEPROM sends
a
zero to
a
cknowledge th
a
t it h
a
s
received e
a
ch word. This h
a
ppens during the ninth clock cycle.
STANDBY MODE:
The AT24C02B fe
a
tures
a
low-power st
a
nd
b
y mode which is
en
ab
led: (
a
) upon power-up
a
nd (
b
)
a
fter the receipt of the
S
TOP
b
it
a
nd the completion
of
a
ny intern
a
l oper
a
tions.
MEMORY RESET:
After
a
n interruption in protocol, power loss or system reset,
a
ny 2-
wire p
a
rt c
a
n
b
e reset
b
y following these steps:
1.
Clock up to 9 cycles.
2.
Look for
S
DA high in e
a
ch cycle while
S
CL is high.
3
.
Cre
a
te
a
st
a
rt condition.
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